Balanced circuitry for reducing inductive noise of external chip interconnections

Abstract

Ground noise associated with lead inductance in electronic systems containing multiple lead integrated circuits is substantially reduced by including, for each chip driver lead that carries a signal, a complementary lead which carries the the inverse of that signal. These balanced pairs are continued not only in the wire bonds and lead frame of the integrated circuit, but also through any connecting assembly such as a printed wiring board or multichip module to the associated balanced chip receivers.

I claim: 
     
       1. An apparatus including A) an integrated circuit with a first multiplicity of electrical drivers with an associated multiplicity of signal outputs leads and electrical interconnects from said multiplicity of output leads wherein said interconnects are external to said integrated circuit and provide electrical communication from said multiplicity of output leads to elements external to said integrated circuit, and B) further including an electrical ground conducting path from said external element to said integrated circuit characterized in that at least 20% of potential error due to noise induced in said ground path by changes in an electrical signal present in at least one of said multiplicity of output leads wherein said noise is compensated for by the presence of a sufficient number of associated secondary leads each corresponding to one of said output leads and said first drivers to transmit a compensating signal on said secondary leads such that the noise induced in said ground path from said compensating signal compensates for said noise introduced by said signal in said output leads. 
     
     
       2. The apparatus of claim 1 wherein the number of said secondary leads is equal to the number of said signal output leads. 
     
     
       3. The apparatus of claim 1 wherein said signal is digital. 
     
     
       4. The apparatus of claim 1 wherein said electrical interconnect comprises a printed wiring board or multichip module. 
     
     
       5. A method of transmitting a plurality of signals from leads of an integrated circuit through electrical interconnects to a plurality of elements, said interconnects and said elements being external to said integrated circuit and compensating for at least 20% of potential errors due to noise induced in a ground path connected between said elements and said integrated circuit said method comprising the step of transmitting a compensating signal on a sufficient number of secondary leads from said integrated circuit to achieve said 20% compensation. 
     
     
       6. The method of claim 5 wherein said signal is digital. 
     
     
       7. The method of claim 5 wherein the number of said secondary leads is equal to the number of said signal leads. 
     
     
       8. The method of claim 5 wherein said electrical interconnect comprises a printed wiring board or multichip module.