Synchro drive stabilization system

Abstract

A system (10) for controlling stabilization of a synchro (26), which is driven from a digital to synchro converter (12), which utilizes a current sensor (14) to detect the magnitude of the synchro current drive signal and through a compare and hold circuit (20) compares the magnitude of the current with a predetermined maximum current and if exceeded provides a signal to a logic control (22) which controls a current limiter (16), disposed in series with the conductors providing load current to synchro (26). Current limiter (16) operates in a non-current limiting mode, wherein load current is passed unhindered to synchro (26), and a current limiting mode wherein current limiting resistors are inserted in series with the conductors carrying drive current to synchro (26). When the commanded drive current exceeds the reference current, compare and hold circuit (20) initiates a signal to cause current limiter (16) to operate in the current limiting mode. Compare and hold circuit (20) also includes a delay circuit which keeps current limiter (16) in the current limiting mode for a short period of time after the commanded drive current falls below the reference current level. A pulse width oscillator (24) provides an input to logic control (22) which causes logic control (22) to periodically switch current limiter (16) to the unlimited current condition for short periods of time even when the compare and hold circuit (20) is providing a signal requesting the current limiting mode.

We claim: 
     
       1. A stabilization system for a synchro which is driven by drive current outputs from a digital signal to synchro signal converter comprising: a current sensor disposed between the synchro and the digital signal to synchro signal converter for sensing the magnitude of the drive current which drives the synchro;   a current limiter disposed between the synchro and the digital signal to synchro signal converter which is operable in a non-current limiting mode permitting the sensed drive current to pass unhindered to the synchro, and a current limiting mode, limiting the sensed drive current provided to the synchro;   compare means for comparing the current signal sensed by said current sensor with a reference current signal and providing a current limiting command signal for initiating switching of said current limiter to the current limiting mode when the sensed current signal exceeds the reference current signal;   switch control means connected to said compare means to receive the current limiting command signal from said compare means for controlling said current limiter to cause said current limiter to switch to a current limiting mode when the sensed current signal exceeds the reference current signal; and,   wherein said compare means includes a hold circuit for providing a signal to keep said current limiter in the current limiting mode for a period of time after the sensed current signal falls below the reference current signal which provides for more stable operation of the synchro by inhibiting said current limiter from repeatedly switching between the current limiting mode and the non-current limiting mode.   
     
     
       2. A system as claimed in claim 1, further comprising pulse width oscillator means for providing a signal to said switch control means which overrides the current limiting command signal from said compare means, for periodic short periods of time, causing said current limiter to periodically allow high current pulses to pass unhindered to the synchro. 
     
     
       3. A method for stabilizing a synchro which is driven by drive current from a digital to synchro converter comprising the steps of: a. disposing a current limiter, which is switchable between a current limiting mode and a non-current limiting mode, between the synchro and the digital to synchro converter;   b. sensing the drive current being fed to said synchro;   c. comparing the sensed synchro drive current with a predetermined referenced level;   d. switching said current limiter to the current limiting mode when the sensed synchro drive current is greater than the predetermined reference level; and   e. periodically switching said current limiter to the non-current limiting mode to periodically supply high current pulses to the synchro during times when the sensed synchro drive current exceeds the predetermined reference level.   
     
     
       4. A method as claimed in claim 3, comprising the further step of: f. maintaining said current limiter in the current limiting mode for a short period of time after the sensed synchro drive current falls beneath the predetermined reference level.   
     
     
       5. A synchro system comprising: a synchro movable to a position in response to AC current signals;   a digital to synchro converter which receives a digital angle command and provides AC current signals for causing said synchro to move to a position;   a current sensor, disposed between said synchro and said digital to synchro converter, which provides a signal indicative of the AC current signals;   compare means connected to said current sensor for comparing the signal indicative of the AC current signals with a reference signal and providing an output when the reference signal is exceeded;   logic means connected to said compare means for providing a control signal in response to the output from said compare means;   a current limiter disposed between said synchro and said digital to synchro converter operable in a current limiting mode wherein current limiting means are disposed between said synchro and said digital to synchro converter for limiting the AC current signals to said synchro and a non-current limiting mode wherein said current limiting means are not utilized and being switchable between said current limiting mode and said non-current limiting mode in response to the control signal from said logic means; and   pulse width oscillator means connected to said logic means for providing an override signal to said logic means for overriding the signal from said compare means causing said logic means to periodically cause said current limiter to switch to the non-current limiting mode and not limit the AC current signals to said synchro.   
     
     
       6. A synchro system as claimed in claim 5 including hold means for keeping said current limiter in the current limiting mode for a period of time after the signal from said current sensor becomes less than the reference signal.