Data interchange network

Abstract

A fiber optic data interchange network comprising a plurality of nodes, or drops 10a, 10b, 10c . . . , interconnected by fiber optic cable 12 (FIG. 1 ). Encoded data signals originating at any node are circulated around the network, allowing multipoint (or multidrop) data interchange. Each node includes a data encoder, transmitter, fiber optic receiver, data decoder, clock recovery circuit, and a repeater, i.e., a combination of the fiber optic receiver, an invertor (providing pulse width distortion correction) and the fiber optic transmitter. Thus each node is capable of originating data transmissions and receiving/relaying transmissions from a preceding node.

What is claimed is: 
     
       1. A drop or node for use in a data interchange network, comprising: (a) receiver means for receiving a first encoded data signal and providing an output signal (RX);   (b) clock recovery means, coupled to said receiver means, for recovering a clock signal (RC) from said output signal RX;   (c) data decoder means, coupled to said receiver means and said clock recovery means, for providing a received data signal (RD) on the basis of said output signal RX and said clock signal RC, said received data signal RD indicative of data encoded in said encoded data signal;   (d) pulse width distortion (PWD) correction means, coupled to said receiver means, for at least partially correcting for any pulse width distortion in said output signal RX and providing a PWD-corrected signal;   (e) encoder means for providing a transmit data signal (XD) on the basis of data to be transmitted (TD) and an externally generated transmit data clock signal (XC);   (f) transmitter means for transmitting a second encoded data signal on the basis of an input signal; and   (g) select means, coupled between said encoder means, PWD correction means and transmitter means, for selectively providing one of either said PWD-corrected signal or said transmit data signal XD as said input signal to said transmitter means.   
     
     
       2. A drop or node as recited in claim 1, wherein said receiver means comprises a fiber optic receiver and said transmitter means comprises a fiber optic transmitter. 
     
     
       3. A drop or node as recited in claim 1, wherein said select means comprises a first tristate-with-enable buffer having an input terminal coupled to an output terminal of said PWD correction means, an output terminal coupled to an input terminal of said transmitter means, and an enable terminal;   an invertor having an output terminal coupled to the enable terminal of said first tristate-with-enable buffer and an input terminal adapted to receive an externally generated request to send signal; and   a second tristate-with-enable buffer having an input terminal adapted to receive the transmit data signal XD, an output terminal coupled to the input terminal of said transmitter means, and an enable terminal adapted to receive said request to send signal.   
     
     
       4. A drop or node as recited in claim 1, wherein said data decoder means comprises: a first flip-flop having a data input terminal (D1) coupled to the receiver means, a clock input terminal (CLK1) coupled to the clock recovery means and an output terminal (Q1);   a second flip-flop having a data input terminal (D2) coupled to the output terminal Q1 of the first flip-flop, a clock input terminal (CLK2) coupled to the clock recovery means and an output terminal (Q2); and   an exclusive OR (EXOR) gate having first and second input terminals coupled to the respective output terminals Q1, Q2 of the first and second flip-flops and an output terminal, wherein the received data signal RD is provided via said output terminal.   
     
     
       5. A drop or node as recited in claim 1, wherein said clock recovery means comprises: a first flip-flop having a data input terminal (D1) coupled to the receiver means, a clock input terminal (CLK1) adapted to receive an externally generated clock signal X16 and an output terminal (Q1);   a second flip-flop having a data input terminal (D2) coupled to the output terminal Q1 of the first flip-flop, a clock input terminal (CLK2) adapted to receive the clock signal X16 and an output terminal (Q2);   an inverted exclusive OR (inverted EXOR) gate having first and second input terminals coupled to the respective output terminals Q1, Q2 of the first and second flip-flops and an output terminal; and   divider means, coupled to the output terminal of the inverted EXOR gate and the respective clock input terminals CLK1, CLK2 of the first and second flip-flops, for providing the clock signal RC on the basis of the clock signal X16 and an output of the inverted EXOR gate.   
     
     
       6. A drop or node as recited in claim 1, wherein said encoder means comprises a Nonreturn to Zero Differential (NRZD) encoder. 
     
     
       7. A drop or node as recited in claim 1, wherein said encoder means comprises a Biphase-mark encoder. 
     
     
       8. A drop or node as recited in claim 6, wherein said NRZD encoder comprises: a first flip-flop having a data input terminal (D1) adapted to accept said data to be transmitted TD, a clock input terminal (CLK1) adapted to accept said transmit data clock signal XC and an output terminal (Q1);   an exclusive OR (EXOR) gate having a first input terminal coupled to the output terminal Q1 of the first flip-flop, a second input terminal and an output terminal; and   a second flip-flop having a data input terminal (D2) coupled to the output terminal of the EXOR gate, a clock input terminal (CLK2) adapted to accept the transmit data clock signal XC and an output terminal (Q2) coupled to the second input terminal of the EXOR gate.   
     
     
       9. A drop or node as recited in claim 1, wherein: said data decoder means comprises:   a first flip-flop having a data input terminal (D1) coupled to the receiver means, a clock input terminal (CLK1) coupled to the clock recovery means and an output terminal (Q1);   a second flip-flop having a data input terminal (D2) coupled to the output terminal Q1 of the first flip-flop, a clock input terminal (CLK2) coupled to the clock recovery means and an output terminal (Q2); and   a first exclusive OR (EXOR) gate having first and second input terminals coupled to the respective output terminals Q1, Q2 of the first and second flip-flops and an output terminal, wherein the received data signal RD is provided via said output terminal;   wherein said clock recovery means comprises:   a third flip-flop having a data input terminal (D3) coupled to the receiver means, a clock input terminal (CLK3) adapted to receive an externally generated clock signal X16 and an output terminal (Q3):   a fourth flip-flop having a data input terminal (D4) coupled to the output terminal Q3 of the third flip-flop, a clock input terminal (CLK4) adapted to receive the clock signal X16 and an output terminal (Q4);   an inverted exclusive or (inverted EXOR) gate having first and second input terminals coupled to the respective output terminals Q3, Q4 of the third and fourth flip-flops and an output terminal; and   divider means, coupled to the output terminal of the inverted EXOR gate and the respective clock input terminals CLK3, CLK4 of the third and fourth flip-flops, for providing the clock signal RC on the basis of the clock signal X16 and an output of the inverted EXOR gate; and   wherein said encoder means comprises:   a fifth flip-flop having a data input terminal (D5) adapted to accept said data to be transmitted TD, a clock input terminal (CLK5) adapted to accept said transmit data clock signal XC and an output terminal (Q5);   a second exclusive or (EXOR) gate having a first input terminal coupled to the output terminal Q5 of the fifth flip-flop, a second input terminal and an output terminal; and   a sixth flip-flop having a data input terminal (D6) coupled to the output terminal of the second EXOR gate, a clock input terminal (CLK6) adapted to accept the transmit data clock signal XC and an output terminal (Q6) coupled to the second input terminal of the second EXOR gate.   
     
     
       10. A drop or node for receiving and re-transmitting, and for originally transmitting, encoded data signals in a fiber optic data interchange network, comprising: (a) a fiber optic receiver adapted to receive a first encoded data signal and providing an output signal (RX);   (b) a clock recovery circuit recovering a clock signal (RC) from said output signal RX, comprising: a first flip-flop having a data input terminal (D1) coupled to the fiber optic receiver, a clock input terminal (CLK1) adapted to receive an externally generated clock signal X16 and an output terminal (Q1);   a second flip-flop having a data input terminal (D2) coupled to the output terminal Q1 of the first flip-flop, a clock input terminal (CLK2) adapted to receive the clock signal X16 and an output terminal (Q2);   an inverted exclusive OR (inverted EXOR) gate having first and second input terminals coupled to the respective output terminals Q1, Q2 of the first and second flip-flops and an output terminal; and   divider means, coupled to the output terminal of the inverted EXOR gate and the respective clock input terminals CLK1, CLK2 of the first and second flip-flops, for providing the clock signal RC on the basis of the clock signal X16 and an output of the inverted EXOR gate;     (c) a data decoder circuit providing a received data signal (RD) on the basis of said output signal RX and said clock signal RC, said received data signal RD being indicative of data encoded in said encoded data signal, said data decoder circuit comprising: a third flip-flop having a data input terminal (D3) coupled to the fiber optic receiver, a clock input terminal (CLK3) coupled to the clock recovery circuit and an output terminal (Q3);   a fourth flip-flop having a data input terminal (D4) coupled to the output terminal Q3 of the third flip-flop, a clock input terminal (CLK4) coupled to the clock recovery circuit and an output terminal (Q4); and   a first exclusive or (EXOR) gate having first and second input terminals coupled to the respective output terminals Q3, Q4 of the third and fourth flip-flops and an output terminal, wherein the received data signal RD is provided via said output terminal;     (d) pulse width distortion (PWD) correction means, coupled to said fiber optic receiver, for at least partially correcting for any pulse width distortion in said output signal RX and providing a PWD-corrected signal;   (e) an encoder circuit for providing a transmit data signal (XD) on the basis of data to be transmitted (TD) and the transmit data clock signal (XC), said encoder circuit comprising: a fifth flip-flop having a data input terminal (D5) adapted to accept said data to be transmitted TD, a clock input terminal (CLK5) adapted to accept said transmit data clock signal XC and an output terminal (Q5);   a second exclusive or (EXOR) gate having a first input terminal coupled to the output terminal Q5 of the fifth flip-flop, a second input terminal and an output terminal; and   a sixth flip-flop having a data input terminal (D6) coupled to the output terminal of the second EXOR gage, a clock input terminal (CLK6) adapted to accept the transmit data clock signal XC and an output terminal (Q6) coupled to the second input terminal of the second EXOR gate;     (f) a fiber optic transmitter adapted to transmit a second encoded data signal on the basis of an input signal; and   (g) select means, coupled between said encoder circuit, PWD correction means and fiber optic transmitter, for selectively providing one of either said PWD-corrected signal or said transmit data signal XD as said input signal to said transmitter.   
     
     
       11. A data interchange network, comprising: (a) a plurality of nodes or drops each of which is capable of receiving, re-transmitting and originally transmitting encoded data signals via fiber optic cable; and   (b) a plurality of cables interconnecting said nodes or drops;   (c) wherein each of said nodes or drops comprises:   (1) receiver means for receiving a first encoded data signal and providing an output signal (RX);   (2) clock recovery means, coupled to said receiver means, for recovering a clock signal (RC) from said output signal;   (3) data decoder means, coupled to said receiver means and said clock recovery means, for providing a received data signal (RD) on the basis of said output signal RX and said clock signal RC, said received data signal RD indicative of data encoded in said encoded data signal;   (4) pulse width distortion (PWD) correction means, coupled to said receiver means, for at least partially correcting for any pulse width distortion in said output signal RX and providing a PWD-corrected signal;   (5) encoder means for providing a transmit data signal (XD) on the basis of data to be transmitted (TD) and an externally generated transmit data clock signal (XC);   (6) transmitter means for transmitting a second encoded data signal on the basis of an input signal; and   (7) select means, coupled between said encoder means, PWD correction means and transmitter means, for selectively providing one of either said PWD-corrected signal or said transmit data signal XD as said input signal to said transmitter means.   
     
     
       12. A data interchange network as recited in claim 11, wherein said cables are fiber optic cables, said receiver means comprises a fiber optic receiver and said transmitter means comprises a fiber optic transmitter. 
     
     
       13. A data interchange network as recited in claim 11, wherein said select means comprises a first tristate-with-enable buffer having an input terminal coupled to an output terminal of said PWD correction means, an output terminal coupled to an input terminal of said transmitter means, and an enable terminal;   an invertor having an output terminal coupled to the enable terminal of said first tristate-with-enable buffer and an input terminal adapted to receive an externally generated request to send signal; and   a second tristate-with-enable buffer having an input terminal adapted to receive the transmit data signal XD, an output terminal coupled to the input terminal of said transmitter means, and an enable terminal adapted to receive said request to send signal.   
     
     
       14. A data interchange network as recited in claim 12, wherein said data decoder means comprises: a first flip-flop having a data input terminal (D1) coupled to the receiver means, a clock input terminal (CLK1) coupled to the clock recovery means and an output terminal (Q1);   a second flip-flop having a data input terminal (D2) coupled to the output terminal Q1 of the first flip-flop, a clock input terminal (CLK2) coupled to the clock recovery means and an output terminal (Q2); and   an exclusive OR (EXOR) gate having first and second input terminals coupled to the respective output terminals Q1, Q2 of the first and second flip-flops and an output terminal, wherein the received data signal RD is provided via said output terminal.   
     
     
       15. A data interchange network as recited in claim 14, wherein said clock recovery means comprises: a third flip-flop having a data input terminal (D3) coupled to the receiver means, a clock input terminal (CLK3) adapted to receive an externally generated clock signal X16 and an output terminal (Q3):   a fourth flip-flop having a data input terminal (D4) coupled to the output terminal Q3 of the third flip-flop, a clock input terminal (CLK4) adapted to receive the clock signal X16 and an output terminal (Q4);   an inverted exclusive OR (inverted EXOR) gate having first and second input terminals coupled to the respective output terminals Q3, Q4 of the third and fourth flip-flops and an output terminal; and   divider means, coupled to the output terminal of the inverted EXOR gate and the respective clock input terminals CLK3, CLK4 of the third and fourth flip-flops, for providing the clock signal RC on the basis of the clock signal X16 and an output of the inverted EXOR gate.   
     
     
       16. A data interchange network as recited in claim 15, wherein said encoder means comprises a Nonreturn to Zero Differential (NRZD) encoder. 
     
     
       17. A data interchange network as recited in claim 15, wherein said encoder means comprises a Biphase-mark encoder. 
     
     
       18. A data interchange network as recited in claim 16, wherein said NRZD encoder comprises: a fifth flip-flop having a data input terminal (D5) adapted to accept said data to be transmitted TD, a clock input terminal (CLK5) adapted to accept said transmit data clock signal XC and an output terminal (Q5);   a second exclusive OR (EXOR) gate having a first input terminal coupled to the output terminal Q5 of the fifth flip-flop, a second input terminal and an output terminal; and   a sixth flip-flop having a data input terminal (D6) coupled to the output terminal of the second EXOR gate, a clock input terminal (CLK6) adapted to accept the transmit data clock signal XC and an output terminal (Q6) coupled to the second input terminal of the second EXOR gate.   
     
     
       19. A method of exchanging data in a network comprising a plurality of nodes or drops and a plurality of cables interconnecting said nodes or drops, the method comprising the steps of: (a) transmitting a first encoded optical data signal from a first node;   (b) receiving said first encoded optical data signal at a second node and providing at said second node an electrical output signal (RX) based upon said first encoded optical data signal;   (c) recovering a clock signal (RC) from said electrical output signal RX;   (d) providing a received data signal (RD), on the basis of said electrical output signal RX and said clock signal RC, indicative of data encoded in said encoded optical data signal;   (e) at least partially correcting for any pulse width distortion (PWD) in said electrical output signal RX and providing a PWD-corrected signal;   (f) generating a transmit data signal (XD) on the basis of data to be transmitted (TD) and an externally generated transmit data clock signal (XC);   (g) selecting one of either said PWD-corrected signal or said transmit data signal XD; and   (h) transmitting, from said second node to a third node, a second encoded optical data signal based upon the selected signal.