Semiconductor memory device having column selection circuit activated subsequently to sense amplifier after first or second period of time

Abstract

The semiconductor memory device according to the present invention has a memory cell array which includes a plurality of memory cells provided in array form and a plurality of bit lines and word lines that are respectively connected to the memory cells, where the bit lines are arranged so as to form a group of paired lines, sense amplifiers which are provided one for each of the bit line pairs, for amplifying the potential difference between the lines of the bit line pair in response to an activating signal, a delay circuit which uses said activating signal as its input signal, for generating a selection signal by giving to said activating signal a delay time that varies in response to a control signal from a switching circuit, and selection switch means for connecting a predetermined one of said bit line pairs and I/O lines in response to said selection signal. When a read error is detected by a function test, the switching circuit is set so as to generate an active level control signal DS, when the read error is eliminated by the setting, it is possible by setting the switching circuit so as to permanently fix the control signal to the active level to convert articles that had to be classified as defective conventionally to conforming articles, thereby making it possible to contribute to an enhancement of the yield.

What is claimed is: 
     
       1. A semiconductor memory device, comprising: a memory cell array including a plurality of word lines, a plurality of bit lines and a plurality of memory cells each connected to one of said word lines and one of said bit lines, a plurality of sense amplifiers each coupled to an associated one of said bit lines and activated by a sense-enable signal to amplify a potential appearing on said associated bit line, a data line through which a read-data signal read out of said memory cell array is transferred in a data read mode and a write-data signal to be written into said memory cell array is transferred in a data write mode, a selection circuit provided between said data line and each of said sense amplifiers and activated by a select-enable signal to form an electrical path between said data line and a selected one of said sense amplifiers, and a delay circuit receiving said sense-enable signal and a control signal and producing said selection-enable signal, said delay circuit delaying said sense-enable signal by a first period of time to produce said select-enable signal when said control signal takes a first logic level and delaying said sense-enable signal by a second period of time to produce said select-enable signal when said control signal takes a second logic level, said first period of time being different from said second period of time. 
     
     
       2. The memory device as claimed in claim 1, further comprising a data amplifier coupled to said data line to receive said read-data signal and a write amplifier coupled to said data line to supply said write-data signal, said data amplifier being activated in response to said select-enable signal in said data read mode, and said write amplifier being activated in response to said select-enable signal in said data write mode. 
     
     
       3. The memory device as claimed in claim 1, wherein said control signal is generated by a switching circuit which includes a fuse and a signal generation circuit, said signal generation circuit generating said control signal with said first logic level when said fuse is blown and with said second logic level when said fuse is not blown. 
     
     
       4. A semiconductor memory device, comprising: a plurality of word lines, a plurality of pairs of bit lines, and a plurality of memory cells each coupled to one of said word lines and one of said pairs of bit lines, a row decoder coupled to said word lines for selecting one of said word lines in response to row address information, a plurality of sense amplifiers each coupled to an associated one of said pairs of bit lines and activated by a sense-enable signal to amplify a potential difference between the associated pair of bit lines, a pair of data lines, a plurality of pairs of selection transistors each coupled between said pair of data liens and an associated one of said sense amplifiers, a column decoder coupled to said pairs of selection transistors for turning one of said pairs of selection transistors ON in response to a selection signal and column address information, and a delay circuit delaying said sense-enable signal and producing a delayed signal, said delayed signal being supplied to said column decoder as said selection signal, said delay circuit delaying said sense-enable signal by a first period of time in a first state and by a second period of time in a second state, said first period of time being different from said second period of time. 
     
     
       5. The memory device as claimed in claim 4, wherein said delay circuit is brought into said first state by a first level of a control signal and into said second state by a second level of said control signal, said control signal being generated by a control circuit including a fuse, said control signal assuming said first level when said fuse is blown and said second level when said fuse is not blown. 
     
     
       6. The memory device as claimed in claim 5, wherein said pair of data lines are coupled to a data amplifier which is activated by said selection circuit in a data read mode and to a write amplifier which is activated by said selection signal in a data write mode.