Circuit for initializing registers using two input signals for writing default value into D-latch after a reset operation

Abstract

A circuit for initializing a D-latch of an input/output system. The circuit comprises first and second logic means, the first logic means generating an enable signal coupled to the clock input of the D-latch which changes state from inactive to active at a first time t1 and again at a subsequent time t2, in response to the system write control signal addressed to the D-latch and the system reset signal. The second logic means generates a local data signal, in response to the system reset signal and system data signal, to the data input of the D-latch. The D-latch is reset substantially at time t1 and the system data signal is strobed in the D-latch substantially at time t2.

We claim: 
     
       1. A circuit for initializing a register of an input/output system, formed on a single integrated circuit chip, said register being reset by a system reset signal from an electronic data processing system after completion of power-on of the electronic data processing system, the electronic data processing system outputting a system write control signal and a system data signal while writing a default value of data to the register, the register having at least one D-latch, said D-latch having a data input, a clock input and a data output, the circuit comprising: a first logic means for generating an enable signal which is coupled to the clock input of the D-latch, said enable signal changing state from inactive to active at a first time t1 and from inactive to active again at a subsequent time t2, in response to the system write control signal addressed to the D-latch and the system reset signal;   a second logic means for generating a local data signal, having as inputs the system reset signal and the system data signal, any an output coupled to the data input of the D-latch;   wherein the D-latch is reset at substantially time t1, and the system data signal is strobed in the d-latch at substantially time t2 while the D-latch is addressed by the electronic data processing system.   
     
     
       2. The circuit in accordance with the claim 1, wherein the first logic means comprising: a delay circuit, the delay circuit having an input, a first output and second output, the system reset signal being coupled to the input, the delay circuit generating a first local reset signal at the first output of the delay circuit by delaying the system reset signal for a first predetermined time delay td1, the delay circuit generating a second local reset signal at the second output of the delay circuit by delaying the system reset signal for a second predetermined time delay td2;   a first AND gate, the AND gate having first input, second input and one output, the first input being coupled to the system write control signal, the second input being coupled to the second local reset signal;   a second AND gate, the AND gate having first input, second input and one output, the first input being coupled to the second local reset signal through an inverter gate, the second input being coupled to the first local reset signal;   a NOR gate, the NOR gate having two inputs and one output, the output of the first AND gate and second AND gate being coupled to one input of the NOR gate respectively;   and wherein the output of the NOR gate being the enable signal of the first logic means.   
     
     
       3. The circuit in accordance with the claim 2, wherein the second logic means comprising: an AND gate, the AND gate having two inputs and one output, the input of the AND gate being coupled to the second local reset signal and system data signal respectively;   and wherein the output being the local data signal of the second logic means.   
     
     
       4. The circuit in accordance with the claim 2, wherein the time delay td1 is less than the time delay td2. 
     
     
       5. The circuit in accordance with the claim 2, wherein the system reset signal, first local reset signal and second local reset signal being active low. 
     
     
       6. The circuit in accordance with the claim 5, the system write signal being active low. 
     
     
       7. The circuit in accordance with the claim 5, wherein the second local reset signal becoming non-active before the system write signal becomes active. 
     
     
       8. The circuit in accordance with the claim 7, wherein the enable signal being active low. 
     
     
       9. The circuit in accordance with the claim 2, wherein the time delay td1 being substantially zero.