Sample data position error signal detection for digital sector servo

Abstract

A sample data position error signal detection means is described. This invention is suited for use in a digital sector servo in a magnetic media disk drive environment. In particular, the invention relates to the detection and presentation in digital form of position error signals (PES) representative of magnitude and sign of recording head displacement from a track centerline. The circuits disclosed provide a digital representation of PES suitable for direct application to a digital signal processor which controls overall servo positioning operations. The invention detects the PES by an integration method and incorporates the innovation of requiring only two integrators to demodulate a PES having an arbitrarily large number of phases. The invention uses a phaselock oscillator having a hybrid digital/analog phase detector to generate the coherent carrier sequence for synchronous detection of PES. A further innovation of the invention is the use of a fully digital automatic gain control circuit (AGC). Prior embodiments of position demodulators have employed analog AGC approaches which are more sensitive to disk surface flaws and which cannot easily be made adaptive. Furthermore, such features as exponentiation of AGC gain control level can be readily incorporated with no penalty to circuit complexity.

I claim: 
     
       1. A circuit for detection of position error signals comprising: synchronous detection means for detecting a position error signal and for providing a first output signal;   first and second integrating means selectably coupled to said detection means for integrating said first output signal, said first and second integrating means providing second and third output signals, respectively;   converting means coupled to said first and second integrating means for converting said second and third output signals from a first signal domain to a second signal domain, thereby generating fourth and fifth output signals, respectively;   storage means couplec to said converting means for storing said fourth and fifth output signals.   
     
     
       2. The circuit of claim 1 wherein said first and second integrating means comprise first and second capacitors. 
     
     
       3. The circuit of claim 2 wherein said first, second and third signals comprise analog signals. 
     
     
       4. The circuit of claim 3 wherein said converting means comprises an analog to digital converter. 
     
     
       5. The circuit of claim 4 wherein said storage means comprises a register file. 
     
     
       6. A circuit for detection of position error signals comprising: synchronous detection means for detecting a position error signal and for providing a first output signal;   first and second integrating means selectably coupled to said detection means for integrating said first output signal, said first and second integrating means providing second and third output signals, respectively, wherein when said first integrating means is integrating, said second integrating means provides said third output signal then resets for subsequent integration and when said second integrating means is integrating, said first integrating means provides said second output signal then resets for subsequent integration.   
     
     
       7. The circuit of claim 6 further comprising converting means coupled to said first and second integrating means for converting said second and third output signals from a first signal domain to a second signal domain, thereby generating fourth and fifth output signals, respectively. 
     
     
       8. The circuit of claim 7 further comprising storage means coupled to said converting means for storing said fourth and fifth output signals. 
     
     
       9. The circuit of claim 8 wherein said storage means comprises a register file. 
     
     
       10. The circuit of claim 7 wherein said converting means comprises an analog to digital converter. 
     
     
       11. The circuit of claim 6 wherein said first and second integrating means comprise first and second capacitors. 
     
     
       12. A circuit for detection of position error signals comprising: detection means for detecting a position error signal and for providing a first output signal;   first and second integrating means selectably coupled to said detection means for integrating said first output signal, said first and second integrating means providing second and third output signals, respectively;   analog to digital converting means coupled to said first and second integrating means for converting said second and third output signals to fourth and fifth output signals, respectively;   storage means coupled to said converting means for storing said fourth and fifth output signals.   
     
     
       13. A circuit for detection of position error signals comprising: synchronous detection means for detecting a position error signal and for providing a first output signal;   first and second integrating means selectably coupled to said detection means for integrating said first output signal, said first and second integrating means providing second and third output signals, respectively;   converting means comprising an analog to digital converter coupled to said first and second integrating means for converting said second and third output signals from a first signal domain to a second signal domain, thereby generating fourth and fifth output signals, respectively.   
     
     
       14. A circuit for detection of position error signals comprising: synchronous detection means for detecting a position error signal and for providing a first output signal;   first and second integrating means selectably coupled to said detection means for integrating said first output signal, said first and second integrating means providing second and third output signals, respectively;   converting means coupled to said first and second integrating means for converting said second and third output signals from a first signal domain to a second signal domain, thereby generating fourth and fifth output signals, respectively;   storage means comprising a register file coupled to said converting means for storing said fourth and fifth output signals.   
     
     
       15. A circuit for detection of position error signals comprising: synchronous detection means for detecting a position error signal and for providing a first output signal;   first and second integrating means selectably coupled to said detection means for integrating said first output signal, said first and second integrating means providing second and third output signals, respectively;   converting means coupled to said first and second integrating means for converting said second and third output signals from an analog form to a digital form, thereby generating fourth and fifth output signals, respectively.   
     
     
       16. A circuit for detection of position error signals comprising: synchronous detection means for detecting a position error signal and for providing a first output signal;   first and second integrating means selectably coupled to said detection means for integrating said first output signal, said first and second integrating means providing second and third output signals, respectively; and   analog-to-digital converter means coupled to said first and second integrating means for producing a digital output responsive to said second and third output signals.   
     
     
       17. The circuit of claim 16 wherein said first and second integrating means comprise first and second capacitors.