Method for dielectrically isolating integrated circuits using doped oxide sidewalls

Abstract

A method for dielectrically isolating a semiconductor integrated circuit is provided. Each integrated circuit is substantially surrounded by silicon oxide sidewalls which have been appropriately doped to be of an opposite conductivity type as the surrounding substrate. The doped silicon oxide sidewalls are formed prior to the growth of epitaxial silicon within the sidewalls. Upon deposition of the epitaxial silicon the dopant within the oxide sidewalls diffuses into the adjacent epitaxial silicon, thereby resulting in a heavily doped, low resistivity region of epitaxial silicon adjacent to and along the entire length of the oxide sidewall. This heavily doped region results in the substantial elimination of charge-depleting parasitic currents along the sidewalls during use of the integrated circuit. In addition, the heavily doped, low resistivity epitaxial region provides an electrically conductive contact to a buried layer within an integrated circuit having such a buried layer. Extremely thin and long, contacts can be made to the buried layer using this method, without the traditional need for long diffusion times which result in excessively wide diffusion zones.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows: 
     
       1. A method for dielectrically isolating an integrated circuit comprising the following steps: providing a silicon substrate having a surface oriented along a single crystallographic plane and characterized by a first electrical conductivity type;   depositing a first layer of silicon oxide onto said surface of said substrate;   patterning said first layer of oxide so as to expose at least one region of said underlying substrate;   etching said at least one exposed region of said silicon substrate so as to form a corresponding number of trenches within said silicon substrate, the integrated circuit being subsequently formed within said trench;   depositing a second layer of silicon oxide on the sidewalls and bottom surface of said trench, said second layer of silicon oxide comprising an appropriate dopant so as to be characterized by an opposite electrical conductivity type as said silicon substrate;   etching said second layer of silicon oxide from said bottom surface of said trench so as to again expose said underlying silicon substrate, wherein the portions of said second layer of silicon oxide deposited on said sidewalls of said trench remain; and   epitaxially growing silicon from said exposed underlying silicon within said trench at a temperature sufficient to effect substantial diffusion of said dopant within said second silicon oxide layer on said sidewalls into an adjacent diffusion region of said epitaxial silicon, said diffusion region of epitaxial silicon being characterized by an electrical conductivity type opposite to said substrate;   wherein the method is effective to dielectrically   isolate the integrated circuit formed within said epitaxial silicon.   
     
     
       2. A method for dielectrically isolating an integrated circuit as recited in claim 1 wherein said silicon substrate is oriented along the [100] crystallographic plane. 
     
     
       3. A method for dielectrically isolating an integrated circuit as recited in claim 1 wherein said silicon substrate is oriented along the [111] crystallographic plane. 
     
     
       4. A method for dielectrically isolating an integrated circuit as recited in claim 1 wherein said silicon substrate is doped to be a P-type electrical conductivity. 
     
     
       5. A method for dielectrically isolating an integrated circuit as recited in claim 1 wherein said about 850° C. 
     
     
       6. A method for dielectrically isolating an integrated circuit as recited in claim 1 wherein said diffusion region of epitaxial silicon is characterized by a dopant level of between about 10 17  atoms/cm 3  and about 10 21  atoms/cm 3 . 
     
     
       7. A method for dielectrically isolating an integrated circuit as recited in claim 1 further comprising prior to said epitaxially growing step an ion implantation step for forming a buried layer within said substrate at said bottom surface of said trench, said buried layer being characterized by an opposite electrical conductivity type as compared to said substrate. 
     
     
       8. A method for dielectrically isolating an integrated circuit while providing an electrical contact to an electrically conductive buried layer within the integrated circuit comprising the following steps: providing a silicon substrate having a surface oriented along a single crystallographic plane and characterized by a P-type electrical conductivity;   depositing a first layer of silicon oxide onto said surface of said substrate;   patterning said first layer of silicon oxide so as to expose at least one region of said underlying substrate;   etching said at least one exposed region of said silicon substrate so as to form a corresponding number of trenches within said silicon substrate, the integrated circuit being subsequently formed within said trench;   depositing a second layer of silicon oxide on the sidewalls and bottom surface of said trench, said second layer of silicon oxide comprising an appropriate dopant so as to be characterized by an N-type electrical conductivity;   etching said second layer of silicon oxide from said bottom surface of said trench so as to again expose said underlying silicon substrate, wherein the portions of said second layer of silicon oxide deposited on said sidewalls of said trench remains;   forming an electrically conductive buried layer within said substrate at said bottom surface of said trench, said buried layer being characterized by an N-type electrical conductivity; and   epitaxially growing silicon from said exposed underlying silicon at said buried layer at a temperature greater than about 850° C. which is sufficient to effect substantial diffusion of said dopant within said second silicon oxide layer on said sidewalls into an adjacent diffusion region of said epitaxial silicon, said diffusion region of epitaxial silicon being characterized by an electrical conductivity type opposite to said substrate;   wherein the method is effective to dielectrically isolate the integrated circuit formed within said epitaxial silicon and concurrently contact said electrically conductive buried layer with a low resistivity, electrical contact at said diffusion region of epitaxial silicon.   
     
     
       9. A method for dielectrically isolating an integrated circuit while providing an electrical contact to a buried layer within the integrated circuit, as recited in claim 8, wherein said silicon substrate is oriented along the [100] crystallographic plane. 
     
     
       10. A method for dielectrically isolating an integrated circuit while providing an electrical contact to a buried layer within the integrated circuit, as recited in claim 8, wherein said silicon substrate is oriented along the [111] crystallographic plane. 
     
     
       11. A method for dielectrically isolating an integrated circuit while providing an electrical contact to a buried layer within the integrated circuit, as recited in claim 8, wherein the portions of said silicon oxide layers removed are removed using reactive ion etching techniques. 
     
     
       12. A method for dielectrically isolating an integrated circuit as recited in claim 8 wherein said diffusion region of epitaxial silicon is characterized by a dopant level of between about 10 17  atoms/cm 3  and about 10 21  atoms/cm 3 . 
     
     
       13. A method for dielectrically isolating an integrated circuit while providing an electrical contact to a buried layer within the integrated circuit, comprising the following steps: providing a silicon substrate having a surface oriented along a single crystallographic plane and characterized by a P-type electrical conductivity;   depositing a first layer of silicon oxide onto said surface of said substrate;   patterning a region of said first layer of silicon oxide so as to expose said underlying silicon substrate, the integrated circuit being subsequently formed within said exposed region;   depositing a second layer of silicon oxide on the sidewalls and bottom surface of said patterned region of said first layer of silicon oxide, said second layer of silicon oxide comprising an appropriate dopant so as to be characterized by an N-type electrical conductivity;   etching said second layer of silicon oxide from said bottom surface so as to again expose said underlying silicon substrate, wherein the portions of said second layer of silicon oxide deposited on said sidewalls remains;   forming a buried layer within said substrate at said bottom surface, said buried layer being characterized by an N-type electrical conductivity; and   epitaxially growing silicon from said exposed underlying silicon at said buried layer at a temperature greater than about 850° C. which is sufficient to effect substantial diffusion of said dopant within said second oxide layer on said sidewalls into an adjacent diffusion region of said epitaxial silicon, said diffusion region of epitaxial silicon being characterized by an electrical conductivity type opposite to said substrate;   wherein the method is effective to dielectrically isolate the integrated circuit formed within said epitaxial silicon and concurrently contact said buried layer with a low resistivity, electrical contact at said diffusion region of epitaxial silicon.   
     
     
       14. A method for dielectrically isolating an integrated circuit while providing an electrical contact to a buried layer within the integrated circuit, as recited in claim 13 wherein said silicon substrate is oriented along the [100] crystallographic plane. 
     
     
       15. A method for dielectrically isolating an integrated circuit while providing an electrical contact to buried layer within the integrated circuit, as recited in claim 13 wherein said silicon substrate is oriented along the [111] crystallographic plane. 
     
     
       16. A method for dielectrically isolating an integrated circuit while providing an electrical contact to a buried layer within the integrated circuit, as recited in claim 13 wherein the portions of said silicon oxide layers removed are removed using reactive ion etching techniques. 
     
     
       17. A method for dielectrically isolating an integrated circuit as recited in claim 13 wherein said diffusion region of epitaxial silicon is characterized by a dopant level of between about 10 17  atoms/cm 3  and about 10 21  atoms/cm 3 .