Ladderless true flash analog-to-digital converter with automatic calibration

Abstract

The true flash analog-to-digital converter has an extremely high speed and resolution. The complexity of the comparators is reduced to an absolute minimum, i.e. one or two transistors, preferably FETs. A reference ladder, e.g. resistor network, is completely eliminated. No matching is necessary. 8-bit converter breaking 1 GHz barrier is possible. The input signal or a reference signal is selectively applied to comparators and compared against base signals stored in capacitors. An encoder is coupled to the comparators for producing the output code. A reference circuit provides the reference signal and a reference code corresponding thereto. A digital comparator compares the code produced by the encoder against the reference code and provides a corrective signal. A demultiplexer applies the corrective signal to one of the capacitors in response to the reference code.

I claim: 
     
       1. Analog-to-digital converter for converting input signal into output code, comprising: a first and second nodes with one node coupled to ground;   a plurality of analog comparator means each comparing a signal at the first node against a respective base signal;   a plurality of capacitor means coupled to the second node for storing the base signals;   a reference means for providing a reference signal and reference code corresponding thereto;   a switch means for selectively coupling the other node to the input signal or reference signal;   an encoder means coupled to the analog comparator means for producing the output code;   a digital comparator means for comparing either a code applied to or produced by the encoder means against the reference code and providing a corrective signal; and   a demultiplexer means for selecting one of the capacitor means and applying the corrective signal thereto in response to the reference code.   
     
     
       2. Analog-to-digital converter of claim 1 wherein at least one analog comparator means includes a transistor having a source and gate electrodes coupled to the firs node and base signal respectively. 
     
     
       3. Analog-to-digital converter of claim 2 wherein the transistor has a drain electrode, and further wherein the one analog comparator means includes a current source means for biasing the drain electrode of the transistor.   
     
     
       4. Analog-to-digital converter of claim 3 wherein the current source means includes a second transistor having a source and gate electrodes coupled to the drain electrode of said first transistor. 
     
     
       5. Analog-to-digital converter of claim 1 wherein the reference means includes an integrator means for providing a ramp signal. 
     
     
       6. Analog-to-digital converter of claim 1 wherein the reference means includes a counter means for providing the reference code. 
     
     
       7. Digital-to-analog converter of claim 1 wherein the reference means includes a shift register means for providing a second reference code, and further wherein the demultiplexer means is responsive to the second reference code.   
     
     
       8. Analog-to-digital converter of claim 1 further including a resistive means coupled to the other node for balancing a current flowing thereto. 
     
     
       9. Analog-to-digital converter of claim 1 wherein the switch means includes an amplifier coupled in series with the other node. 
     
     
       10. Analog-to-digital converter of claim 1 further including a second switch means for selectively coupling the one node to ground or reference signal, wherein said first switch means selectively couples the other node to the input signal or ground.   
     
     
       11. Analog-to-digital converter of claim 1 wherein the digital comparator means provides a corrective current having a determinable polarity. 
     
     
       12. Analog-to-digital converter of claim 1 wherein the encoder has a first output, and further including: a second analog-to-digital converter means having a second output, for converting the input signal into a second output code; and   a multiplexer means for selecting the first or second output and providing the output code.   
     
     
       13. Analog-to-digital converter of claim 12 further including: a second switch means for selectively applying the reference signal or input signal to the second analog-to-digital converter means; and   a second multiplexer means for selectively coupling the first or second output to the digital comparator means.   
     
     
       14. Analog-to-digital converter of claim 13 wherein the second switch means includes an amplifier coupled in series with the second analog-to-digital converter means.