Rank cell array structure for sorting by each cell comparing the cell value to previous cell value, next cell value, in value and out value

Abstract

A rank cell array for ranking a series of sample values including a number of identical rank cells (RC1, RC2. . . ) permitting ready modification of the sorting window size in an OS CFAR radar application, for example. Each rank cell (RC1, RC2. . . ) includes a multiplexer (49), a D flip-flop (41), first and second comparators (43, 45), and a multiplexer controller (49). Each clock interval, the foregoing circuitry examines the sample value entering the sorting window, the sample value leaving the sorting window, the sample value in the preceding rank cell, and the sample value in the succeeding rank cell to determine the sample value in the rank cell during the next clock interval.

What is claimed is: 
     
       1. A rank cell array structure constructed with identically structured, successively arranged rank cells wherein each respective rank cell stores a sample and wherein said array receives a new sample in each of a plurality of successive clock intervals, each rank cell comprising: a multiplexer means receiving as inputs the sample in the preceding rank cell, the sample in the succeeding rank cell, the new sample, and the sample in the respective rank cell, said multiplexer means being responsive to a control signal for outputting one of said samples;   a flip-flop means for storing and outputting the sample in the respective rank cell;   a first comparator means for comparing the sample in the respective rank cell to the new sample and providing a first comparator output;   a second comparator means for comparing an out sample to the sample in the respective rank cell and providing greater than and equal to comparator outputs; and   control logic means responsive to the first, second and third comparator outputs and to the respective preceding and succeeding outputs of the first comparator means of each of the rank cell means preceding and succeeding said respective rank cell in said array to generate said control signal.   
     
     
       2. The circuitry of claim 1 wherein said control logic means comprises: inverter means for inverting said first, second and third comparator outputs to produce inverted values thereof; and   logic means supplied with said inverted values, said first and second comparator outputs and said succeeding output for producing said control signal.   
     
     
       3. The circuitry of claim 2 wherein said logic gate means comprises: NAND gate means receiving as inputs said inverted values, said first and second comparator outputs and said succeeding output for providing a plurality of outputs;   AND gate means receiving the plurality of outputs of said NAND gate means and said succeeding output as inputs and providing first and second outputs; and   inverter means receiving the first and second outputs of said AND gate means and providing first and second outputs.