Process for fabricating self-aligned metal gate field effect transistors

Abstract

A method of fabricating a metal-gate field effect transistor having source and drain regions which are self-aligned with the gate. The source and drain dopants are introduced into the substrate and driven. Then, a metal gate is formed, the metal gate having a length which is approximately the same as the length of the channel. After the gate is fabricated, dopant ions are implanted into any portions of the channel not covered by the gate. These dopant ions are activated by rapid thermal annealing at a temperature selected to avoid damage to the metal gate, to form bridge regions which extend one or both of the source/drain regions into the channel and which are self-aligned with the gate.

We claim: 
     
       1. A method for fabricating a metal gate field effect transistor in a substrate, comprising the steps of: (a) providing two source/drain regions in the substrate, the source/drain regions being spaced apart to define a channel therebetween;   (b) providing a gate oxide overlaying the source/drain regions and the channel;   (c) providing a metal gate overlying a first portion of the channel;   (d) providing dopant ions in a second portion of the channel using he metal gate provided in said step (c) as a mask; and   (e) activating the dopant ions provided in said step (d) by rapid thermal annealing at temperatures between approximately 400° C. and 650° C. for a time between approximately 5 seconds and approximately 45 seconds and (ii) furnace annealing at a temperature less than or equal to 500° C. or a time between approximately 10 minutes and 30 minutes to form a bridge region which is self-aligned with the metal gate and which extends one of the source/drain regions laterally into the channel.   
     
     
       2. A method according to claim 1, wherein the channel has an N-type conductivity and said step (d) comprises implanting boron ions at an energy between approximately 50 keV and 150 keV and to a dopant density between approximately 1×10 12  cm -2  and approximately 1×10 16  cm -2 . 
     
     
       3. A method according to claim 2, wherein said step (d) comprises implanting boron ions to a dopant density of approximately 1×10 15  cm -2 . 
     
     
       4. A method according to claim 1, wherein step (e) comprises activating the dopant ions provided in said step (d) by rapid thermal annealing to form two bridge regions which are self-aligned with the metal gate nd which extend corresponding ones of the source/drain regions laterally into the channel. 
     
     
       5. A method according to claim 1, wherein said step (e) comprises rapid thermal annealing at temperatures between approximately 500° C. and approximately 550° C. 
     
     
       6. A method according to claim 1, wherein the channel has an P-type conductivity and said step (d) comprises implanting phosphorus dopant ions at an energy between approximately 80 keV and approximately 250 keV and to a dopant density between approximately 1×10 12  cm -2  and approximately 1×10 16  cm -2 . 
     
     
       7. A method according to claim 4, wherein the channel has an P-type conductivity and said step (d) comprises implanting phosphorus dopant ions at an energy between approximately 80 keV and approximately 250 keV and to a dopant density between approximately 1×10 12  cm -2  and approximately 1×10 16  cm -2 . 
     
     
       8. A method according to claim 7, wherein said step (d) comprises implanting phosphorus ions to a dopant density of approximately 1×10 13  cm -2 . 
     
     
       9. A method according to claim 6, wherein said step (d) comprises implanting phosphorus ions to a dopant density of approximately 1×10 13  cm -2 . 
     
     
       10. A method according to claim 4, wherein the channel has an N-type conductivity and said step (d) comprises implanting boron ions at an energy between approximately 50 keV and 150 keV and to a dopant density between approximately 1×10 12  cm -2  and approximately 1×10 16  cm -2 . 
     
     
       11. A method according to claim 10, wherein said step Z(d) comprises implanting boron ions to a dopant density of approximately 1×10 15  cm -2 . 
     
     
       12. A method of fabricating a metal gate field effect transistor in a substrate, comprising the step of: (a) providing two source/drain regions in the substrate, the source/drain regions being spaced apart to define a channel therebetween, the channel having a length L;   (b) providing a gate oxide overlying the source/drain regions and the channel;   (c) provide in a metal gate overlying at least a first portion of the channel, the first portion of the channel having a length M, where M is approximately equal to or less than L;   (d) implanting dopant ions in a second portion of the channel after said step (c); and   (e) activating the dopant ions provided in said step (d) (i) by rapid thermal annealing at temperatures between approximately 500°0 C. and 550° C. for a time between approximately 5 seconds and approximately 45 seconds, and (ii) furnace annealing at a temperature less than or equal to 500° C. for a time between approximately 10 minutes and 30 minutes to form a bridge which extends a source/drain region laterally into the second portion of the channel and which is elf-aligned with the metal gate.   
     
     
       13. A method according to claim 12, wherein step (e) comprises activating the dopant ions provided in said step (d) by rapid thermal annealing to form two bridge regions which are self-aligned with the aluminum gate and which extend corresponding ones of the source/drain regions laterally into the channel. 
     
     
       14. A method of fabricating a metal gate field effect transistor in a substrate, comprising the steps of: (a) providing tow source/drain regions in the substrate, the source/drain regions being spaced apart to define a channel therebetween, the channel having a length L;   (b) providing a gate oxide overlying the source/drain regions and the channel;   (c) providing an aluminum gate overlying at least a portion of the channel, the aluminum gate having a length M, where M is approximately equal to or less than L;   (d) providing dopant ions in a second portion o the channel using the aluminum gate as a mask; and   (e) actuating the dopant ions provided in said step (d) (i) by rapid thermal annealing at temperatures between approximately 500° C. and 550° c. for a time between approximately 5 seconds and approximately 45 seconds and (ii) furnace annealing at a temperature less than or equal to 500° C. for a time between approximately 10 minutes and 30 minutes to form a bridge which extends a source/drain region laterally into the second portion of the channel and which is self-aligned with the aluminum gate.   
     
     
       15. A method according to claim 14, wherein step (e) comprises activating the dopant ions provided in said step (d) by rapid thermal annealing to form two bridge regions which are self-aligned with the aluminum gate and which extend corresponding ones of the source/drain regions laterally into the channel. 
     
     
       16. A method of fabricating a metal gate field effect transistor in a substrate, comprising the steps of: (a) providing a source and a drain region in the substrate, the source and rain regions being spaced apart to define a channel therebetween, the channel having a length L;   (b) providing a gate oxide overlying the source/drain regions and he channel;   (c) providing a metal gate overlying a first portion of the channel, the metal gate having a length M, where M is approximately L/2;   (d) providing dopant ions in a second portion and a third portion of the channel using the metal gate as a mask; and   (e) activating the dopant ions provided in said step (d) (i) by rapid thermal annealing at temperatures between approximately 500° C. and 550° c. or a time between approximately 5 seconds and approximately 45 seconds and (ii) furnace annealing at a temperature less than or equal to 500° C. for a time between approximately 10 minutes and 30 minutes to form a first bridge in the second portion of the channel and to form a second bridge in the third portion of the channel, the first and second bridges being self-aligned with the metal gate.   
     
     
       17. A method according to claim 16, wherein step (e) comprises activating the dopant ions provided in said step (d) by rapid thermal annealing. 
     
     
       18. A method of fabricating CMOS field effect transistor in a substrate having N-type conductivity and a surface, comprising the steps of: (a) growing a first oxide layer on the surface of the substrate;   (b) removing a first selected portion of he first oxide layer corresponding to a region where a P-well is to be formed;   (c) forming a P-well by implanting P-type dopant ions in the substrate using the portions of the first oxide layer remaining after said step (b) as a mask;   (d) annealing the structures formed in said steps (a)-(c) to activate the dopant ions implanted in said step (c) and to grow a second oxide labyrinth regions where the first oxide layer was removed in said step (b);   (e) implanting P-type dopant ions using the portions of the first oxide layer remaining after said step (d) and the second oxide layer as masks;   (f) implanting N-type dopant using the portions of the first oxide layer remaining after said step (e) an eh second oxide layer as masks;   (g) annealing the structures formed in said steps (a)-(f) to activate the dopants implanted in steps (e) and (f) to form P-type and N-type source/drain regions, the P-type source/drain regions being spaced apart to define a first channel of length L 1  therebetween and the N-type source/drain regions being spaced apart to define a second channel of length L 2  therebetween nd to grow a third oxide layer;   (h) removing selected portions of the third oxide layer to expose portions of the surface of the substrate corresponding to the channel regions;   (i) forming first and second aluminum gates, the aluminum gates overlying at least a portion of each of the respective first and second channel regions;   (j) implanting in the first channel a P-type dopant using the first aluminum gate as a mask;   (i) implanting in the second channel an N-type dopant using the second aluminum gate as a mask; and   (l) activating the dopants implanted in steps (j) and (k) by rapid thermal annealing at a temperature between 500° C. and 550° C. for a time less than approximately 45 seconds to form a P-type bridge in the first channel and an N-type bridge in the second channel, each o the bridges extending a corresponding source/drain region laterally into the respective channel and being self-aligned with the respective aluminum gate.   
     
     
       19. A method according to claim 12, wherein said step (i) comprises forming a first aluminum gate having a length M 1 , where L 1  is greater than M 1  and forming a second aluminum gate having a length M- 2 , where L 2  is greater than M 2 . 
     
     
       20. A method according to claim 19, whereby said step (l) comprises forming two P-tyep bridges extending corresponding ones of the P-type source/drain regions laterally into the first channel, the P-type bridges being self-aligned with the first aluminum gate, and forming two N-type bridges extending corresponding ones of the N-type source/drain regions laterally into the second channel, the N-type bridges being self-aligned with the second aluminum gate. 
     
     
       21. A method according to claim 19, wherein said step (i) comprising forming a first aluminum gate having a length M 1 , where L 1  is approximately equal to or less than M 1  and forming a second aluminum gate having a length M 2 , where L 2  is approximately equal to or less than M 2 . 
     
     
       22. A method according to claim 21, whereby said step (l) comprises forming one P-type bridge extending one of the P-type source/drain regions laterally into the first channel, the P-tyep bridge being self-aligned with he first aluminum gate, and forming one N-type bridge extending one of the N-type source/drain regions laterally into the second channel, the N-type bridge being self-aligned with the second aluminum gate. 
     
     
       23. A method of fabricating CMOS field effect transistor according to claim 19, wherein said step (l) comprises forming two P-type bridges extending corresponding ones of the P-tyep source/drain regions laterally into he first channel, the P-type bridges being self-aligned with he first aluminum gate, and forming one N-type bridge extending one of the N-type source/drain regions laterally into the second channel, the N-type ridge being self-aligned with the second aluminum gate.