Improved cpu pipeline having register file bypass and working register bypass on update/access address compare

Abstract

An A output and a B output of a register file 16 are each provided to an associated multiplexer (18,20). Each multiplexer has as a further input a bus (CB00:31) that conveys a result from an ALU 22 via an ALU shifter 28. Outputs of the multiplexers are provided to corresponding A or B inputs of the ALU. Each multiplexer is controlled by an associated register file address comparator (24,26). The address comparators each have as an input corresponding register file A and B update and access addresses. The address comparators compare their associated register file update and access addresses to determine if the register file register selected for access is equal to the register file register selected for update. If these two addresses are found to be equal it is indicated that the result of an ALU operation during an instruction cycle N is to be used as an operand for an ALU operation during a cycle N+1. When this condition is detected the output of the associated address comparator enables the corresponding multiplexer select input to gate the ALU result directly to the corresponding input of the ALU, thereby effectively bypassing the register file.

What is claimed is: 
     
       1. A method for operating an arithmetic pipeline of the type that includes a local addressable store means having a plurality of locations for storing operands, the pipeline including working register means accessed separately from the store means for storing temporary results of operations on the operands, the pipeline further comprising ALU means having inputs for receiving a first operand and a second operand from the store means or from the working register means, the ALU means having an output for expressing the result of an operation performed upon the first operand and the second operand, the method comprising the steps of: during a first time interval addressing the store means to retrieve the first operand and a second operand therefrom;   applying the first operand and the second operand to an A input and to a B input, respectively, of the ALU means to produce at an ALU means output a temporary result for storage within a first working register means or a second working register means, the first working register having an input coupled to the output of the ALU and an output coupled to the A input of the ALU, the second working register having an input coupled to the output of the ALU and an output coupled to the B input of the ALU;   during a second time interval determining if a next operation requires for either a first operand or a second operand the result or the temporary result produced during the first time interval; and   if the result or the temporary result produced during the first time interval is determined to be required for the next operation for either the first operand or the second operand, the method includes the steps of uncoupling the ALU means A input from the store means and from the first working register means, and coupling the ALU means output to the A input of the ALU means for providing the result or the temporary result thereof, or   uncoupling the ALU means B input from the store means, and from the second working register means, and coupling the ALU means output to the B input of the ALU means for providing the result or temporary result thereto.   
     
     
       2. A method as set forth in claim 1 wherein the step of determining during a second time interval includes a step of comparing an update address associated with the store means to an access address associated with the store means to detect if the two address are equal. 
     
     
       3. A method as set forth in claim 1 wherein the steps of coupling and uncoupling include a step of activating a multiplexer means to select an input having the ALU means result coupled thereto for coupling the input to an output of the multiplexer means, the output of the multiplexer means being coupled to an input of the ALU means. 
     
     
       4. A method as set forth in claim 1 wherein step of determining during a second time interval includes a step of detecting if an update signal for the working register means is asserted in conjunction with an access signal for the working register means. 
     
     
       5. Data processing apparatus comprising an arithmetic pipeline of the type having a local addressable store means having a plurality of locations for storing operands, the pipeline further comprising ALU means having inputs for receiving a first operand and a second operand from a first output and from a second output, respectively, of the store means, the ALU means having an output for expressing the result of an operation performed upon the first operand and the second operand, the apparatus further comprising: first working register means accessed separately from the store means for storing temporary results of operations on the operands, the first working register means having an input coupled to the output of the ALU means and an output coupled to a first input of the ALU means;   second working register means accessed separately from the store means for storing temporary results of operations on the operands, the second working register means having an input coupled to the output of the ALU means and an output coupled to a second input of the ALU means;   means for addressing the store means during a first time interval to retrieve a first operand and a second operand therefrom;   means for applying the first operand and the second operand to the first input and to the second input, respectively, of the ALU means to produce at an ALU means output a result or a temporary result;   means for determining during a second time interval if the ALU means requires for either the first operand or the second operand the result or the temporary result produced during the first time interval; and   means, coupled to and responsive to the operation of the determining means, for uncoupling one of the ALU inputs from the output of the store means and from the output of the associated working register means and for coupling the ALU means output to either the A input or the B input of the ALU means if a next operation requires for either the first operand or the second operand the result or the temporary result produced during the first time interval.   
     
     
       6. Data processing apparatus as set forth in claim 5 wherein the determining means comprises comparator means for comparing an update address associated with the store means to an access address associated with the store means to detect if the two addresses are equal. 
     
     
       7. Data processing apparatus as set forth in claim 5 wherein the coupling means comprises multiplexer means having the ALU means output coupled to an input thereof, an output of the multiplexer means being coupled to one of the inputs of the ALU means. 
     
     
       8. Data processing apparatus as set forth in claim 5 wherein the determining means comprises means for detecting if an update signal for the working register means is asserted in conjunction with an access signal for the working register means. 
     
     
       9. Data processing apparatus as set forth in claim 5 wherein the store means is comprised of register file means organized as n locations each comprised of m bits, a particular one of the n locations being specified by a register file update address and/or by a register file success address. 
     
     
       10. Data processing apparatus as set forth in claim 5 wherein the determining means is responsive to signals generated as a result of decoding a microinstruction. 
     
     
       11. Apparatus for performing arithmetic/logical operations upon digital operands to produce a digital result, comprising: means having a plurality of storage locations for storing digital data expressive of operands, said storing means having a data input for receiving an operand to be stored at an address specified by an update address input, said storing means further having a first output for providing a first operand therefrom and a second output for providing a second operand therefrom, the storage locations of the first and the second operands being specified by a first access address and by a second access address, respectively;   ALU means, for operating on a first operand and on a second operand to produce a result of a temporary result therefrom, said ALU means having a first input coupled to said first output of said storing means and a second input coupled to said second output of said storing means for receiving the first operand and the second operand, respectively, therefrom, said ALU means further having an output for providing the result or the temporary result therefrom, said ALU means output being coupled to said input of said storing means for providing the result thereto for storage therein;   first working register means having an input coupled to the ALU means output for receiving a temporary result therefrom and having output coupled to the first input of the ALU means for providing the temporary result thereto;   second working register means having an input coupled to the ALU means output for receiving a temporary result therefrom and having an output coupled to the second input of the ALU means for providing the temporary result thereto;   first means for selecting either said first output of said storing means, said output of said first working register means, or said output of said ALU means for input to said first input of said ALU means; and   second means for selecting either said second output of said storing means, said output of said second working register means, or said output of said ALU means for input to said second input of said ALU means.   
     
     
       12. Apparatus as set forth in claim 11 wherein the first and the second selecting means are each responsive to an operation of a comparator means that compares the update address associated with the storing means to the access addresses associated with the storing means to detect if an equality exists such that, if the update address does equal one of the access addresses, the associated one of the selecting means couples the output of the operating means to the associated input of the operating means. 
     
     
       13. Apparatus as set forth in claim 11 wherein the first and the second selecting means are each responsive to an operation of a detecting means that detects if an update signal for either the first or the second working register means is asserted in conjunction with an access signal for the associated working register means such that, if the update signal is asserted in conjunction with the access signal, the associated one of the selecting means couples the output of the operating means to the associated input of the operating means.