Control device for particle accelerator

Abstract

A plural of memories for storing a variation of current flowing through a particle accelerator coil over one period of operation as an operation pattern are provided, to which clock pulses are supplied cylically with the above period as a unit to read the operation pattern in synchronism with the clock pulses to thereby control the accelerator coil current. A rewriting of operation pattern to be stored in the respective memories is performed in a period during which the clock pulses are not supplied.

What is claimed is: 
     
       1. A control device of a particle accelerator, said accelerator having at least one particle accelerator coil, said control device comprising, a power source for supplying current to said coil;   a pulse generator for producing clock pulses;   a plurality of memory means for storing time variation of current flowing through said coil as an operation pattern;   means for reading said operation pattern stored in the selected one of said plurality of memory means in synchronism with said clock pulses from said pulse generator;   an output circuit for supplying said operation pattern read out by said reading means to said power source; and   means for rewriting an operation pattern to be stored in said memory means to which no clock pulses are supplied.   
     
     
       2. The control device claimed in claim 1, further comprising a switch means for selectively supplying said clock pulses from said pulse generator to one of said plurality of memory means. 
     
     
       3. The control device claimed in claim 2, wherein said switch means supplies said clock pulses cyclically to each of said plurality of memory means with a predetermined sequence, respectively. 
     
     
       4. The control device claimed in claim 1, wherein said output circuit comprises logical sum circuits connected to each of said plurality of memory means. 
     
     
       5. The control device claimed in claim 2, further comprising a control computer for controlling said pulse generator, said switch means and said plurality of memory means. 
     
     
       6. The control device claimed in claim 2, wherein said switch means comprises switch elements connected in series with an input of each of said plurality of memory means and means for cyclically turning on said switch elements in a predetermined sequence.