Integrated circuit integrity testing apparatus

Abstract

Each component circuit of an LSI wafer includes a kernel logic section that checks the integrity of the circuit to which it belongs according to a step-by-step process by which progressively larger portions of the circuit are tested. Logic tested during one step is involved in the next step, and once testing of the component circuit is completed, it is extended to testing adjacent circuits of the wafer. Detection of a fault at any stage results in isolation of the faulty circuit or part of it. Test programs and data are stored in ROM within the component circuit, or are supplied via wires bonded to the wafer, for storage in RAM. On completion of the testing, configuration logic within the circuits interconnects the good circuits in an array for communication of signals between them. The kernel logic may be shared between groups of component circuits.

I claim: 
     
       1. In an integrated circuit in which a multiplicity of semiconductor regions of a unitary substrate each contain a component circuit that is adapted to carry out a data function and to transfer signals to, and to receive signals from, others of the circuits, each component circuit includes means to derive a control condition in dependence upon signal responses that occur within the individual circuit according to the integrity of circuitry therein, and means to enable interconnections of the component circuit with others of said component circuits for the purposes of the transfer and reception of signals between them, in dependence upon the derived control condition, the improvement wherein each said region includes logic circuitry individual to the respective region and operable for determining circuit integrity within that region to derive said control condition in accordance therewith, and said logic circuitry in each region includes means for checking circuit integrity within the respective region by a process which comprises a plurality of successive testing steps that involve progressively extended portions of the region, said checking means comprising a kernel logic section and said process beginning from said kernel logic section without test of its integrity. 
     
     
       2. An integrated circuit according to claim 1 wherein said process provides that after each successive testing step is performed, circuitry of the portion of the region tested during that step, is included in the testing of the next portion to be tested. 
     
     
       3. An integrated circuit according to claim 1 wherein said kernel logic section is involved in each testing step of the process sequence. 
     
     
       4. An integrated circuit according to claim 3 wherein said kernel logic section comprises a microprocessor and registers. 
     
     
       5. An integrated circuit according to claim 3 wherein operation of said kernel logic section of the logic circuitry is serial. 
     
     
       6. An integrated circuit according to claim 1 wherein the logic circuitry of each said region comprises means to test the integrity of the circuitry of at least one other of said regions following completion of the testing of its own region. 
     
     
       7. An integrated circuit according to claim 1 wherein each region includes read-only memory, and means for reading program from the read-only memory, and wherein the logic circuitry of each region comprises means to act for at least part of the sequence of testing steps, in accordance with the program read from the read-only memory of its said region. 
     
     
       8. An integrated circuit according to claim 1 including program-supply means for supplying program signals to the logic circuitry of each region from outside said regions, and wherein the logic circuitry of each region comprises means to act for at least part of the sequence of testing steps, in accordance with program supplied to the said region via said program-supply means. 
     
     
       9. An integrated circuit according to claim 1 including means in each region to respond to the condition in which the integrity check is satisfied within that region to interconnect the component circuit of that region with the component circuits of other regions for which the integrity check is satisfied, this interconnection of the component circuits connecting them together in an array for transfer of signals to, and reception of signals from, one another in that array. 
     
     
       10. An integrated circuit according to claim 8 wherein said program-supply means comprises conductors bonded at intervals only, to the substrate. 
     
     
       11. An integrated circuit comprising a multiplicity of component-circuit means for carrying out data operations, each of said component circuit means including: (a) logic circuitry which includes a logic section that is operable to carry through from itself a step-by-step integrity-checking process within the respective circuit means to derive in dependence upon the result of the process a control condition indicative of integrity of the individual circuit means; and   (b) configuration circuitry operable in response to said control condition to enable interconnection of the respective circuit means with others of said circuit means for signal interchange therewith, wherein the integrity-checking process performed by the logic section of each said circuit means comprises a sequence of steps in which the logic section is involved successively in checking the integrity of progressively larger portions of that circuit means, and each integrity-checking step involves checking the integrity of the subject portion of the circuit means against a criterion based on a premise of inherent integrity of said logic section.     
     
     
       12. An integrated circuit according to claim 11 wherein each logic section comprises a microprocessor and at least one register. 
     
     
       13. An integrated circuit according to claim 11 wherein each logic section includes a hard-wired program, and wherein the first step of the integrity-checking process includes exercise of said hard-wired program to check a first portion of said circuit means. 
     
     
       14. An integrated circuit according to claim 13 wherein each said circuit means includes a memory section, and the logic section of that circuit means is operative during said first step of the integrity-checking process to read out words from the memory section and to test them according to said hard-wired program. 
     
     
       15. An integrated circuit according to claim 14 wherein the logic section of each said circuit means is operative during at least the second step of said process to read integrity-testing program from the memory section of that circuit means, said logic section also being operative to apply this program to the testing of a portion of the circuit means which extends beyond said logic and memory sections. 
     
     
       16. An integrated circuit according to claim 11 wherein each said circuit means is an individual component circuit which comprises said logic circuitry, said configuration circuitry, functional circuitry for processing data, and memory means. 
     
     
       17. An integrated circuit according to claim 11 wherein each said circuit means comprises a plurality of component circuits, each said component circuit comprising logic means, circuit-configuration means for interconnecting the component circuit with others of said component circuits, functional circuitry for processing data, and memory means.