Semiconductor static ram including load resistors formed on different layers

Abstract

A static random access memory device including resistance loaded flip-flop circuits has adjacent memory cells arranged to form memory cell pairs. Each memory cell pair has a first unit cell and a second unit cell. Load resistors for the first unit cells and load resistors for the second unit cells are formed on different insulation layers and are stacked on each other on the substrate. A structural pattern of the load resistors is extended over adjacent memory cells in order for the length and resistance of the resistors to be increased. The length of the load resistors can be cut down for compensating for the increase in the resistance enabling the reduction in size of other devices, and enabling the packing density of the device to be increased.

I claim: 
     
       1. A semiconductor static random access memory device formed on a semiconductor substrate and a plurality of insulation layers formed over said semiconductor substrate, said semiconductor static random access memory device, comprising: a plurality of unit cell pairs, wherein each of said unit cell pairs includes a first unit cell and a second unit cell which are arranged adjacent in a data-line direction, each first unit cell and each second unit cell comprises a flip-flop which is formed by a pair of inverter circuits, each inverter circuit includes a field effect transistor formed on said substrate and a load resistor, and load resistors of each first unit cell and load resistors of each second unit cell are formed on different insulation layers and have respectively a layer pattern extending over a substrate surface of an adjacent unit cell within each of said unit cell pairs.   
     
     
       2. The semiconductor static random access memory device as set forth in claim 1, wherein said load resistors are made from a material selected from a group consisting of silicon carbide and amorphous silicon. 
     
     
       3. The semiconductor static random access memory device as set forth in claim 1, wherein said load resistors are made of molybdenum alloy. 
     
     
       4. The semiconductor static random access memory device as set forth in claim 1, wherein each of said first unit cells further comprises a first voltage source line for supplying a source voltage to that first unit cell, wherein each of said second unit cells further comprises a second voltage source line for supplying the source voltage to that second unit cell, wherein each first voltage source line is formed on a first insulation layer which is formed over said substrate, wherein load resistors of each first unit cell are formed on a third insulation layer which is formed over said first insulation layer, wherein each second voltage source line is formed on a second insulation layer which is formed over said third insulation layer, and wherein load resistors of each second unit cell are formed on a fourth insulation layer which is formed over said second insulation layer. 
     
     
       5. The semiconductor static random access memory device as set forth in claim 1, wherein each of said first unit cells further comprises a first voltage source line for supplying a source voltage to that first unit cell, wherein each of said second unit cells further comprises a second voltage source line for supplying a source voltage to that second unit cell, wherein load resistors of each first unit cell and each first voltage source line are formed on a first insulation layer formed over said substrate, and wherein load resistors of each second unit cell and each second voltage source line are formed on a second insulation layer which is formed over said first insulation layer. 
     
     
       6. The semiconductor static random access memory device as set forth in claim 5, wherein each of said unit cells further comprises a transfer transistor having an FET formed on said substrate and said transfer transistor is positioned at outside regions of each of said unit cell pairs in the data-line direction, said transfer transistor sending out information on whether an associated inverter is in a high state or a low state to an outer circuit, and wherein load resistors formed on said second insulation layer are longer than load resistors formed on said first insulation layer. 
     
     
       7. The semiconductor static random access memory device as set forth in claim 4 or 6, wherein the thickness of each of said load resistors is thinner than the thickness of either of said first and second voltage source lines. 
     
     
       8. The semiconductor static random access memory device as set forth in claim 1, 4, 5 or 6, wherein said substrate is a silicon substrate, and wherein each insulation layer is a silicon dioxide layer. 
     
     
       9. The semiconductor static random access memory device as set forth in claim 4, 5 or 6, wherein said load resistors and said first and second voltage source lines are made from polysilicon. 
     
     
       10. The semiconductor static random access memory device as set forth in claim 9, wherein said load resistors and said first and second voltage source lines are ionimplanted to increase conductivity. 
     
     
       11. The semiconductor static random access memory device as set forth in claim 9, wherein said load resistors and said first and second voltage source lines are doped to increase conductivity.