Semiconductor device having output buffer circuit controlled by output control signal

Abstract

In a semiconductor circuit device having a data output buffer circuit for driving an external circuit under the control of an output control signal, the device comprises an output detecting circuit for detecting the level changes in the data signal which is inputted to the data output buffer circuit. The output detecting circuit may also detect the level changes in the output control signal. The device further comprises a holding circuit for holding the output level of other related input circuits, for example an external signal input circuit, based on the detection of the level changes by the output detecting circuit, whereby possible output noises attendant on the data outputting operation of the data output buffer circuit are prevented from affecting the operation of the other related input circuits.

What is claimed is: 
     
       1. A semiconductor device having a data output buffer circuit controlled by an output control signal, comprising: an output detecting circuit for detecting the level changes in the data signal inputted to said data output buffer circuit;   a signal input circuit, an output level of which is determined on the basis of the detection of the level changes in the data signal by said output detecting circuit; and   a holding circuit for holding said output level of said signal input circuit,   whereby possible output noises attendant on the data outputting operation of said data output buffer circuit are prevented from affecting the operation of said signal input circuit.   
     
     
       2. A semiconductor device according to claim 1, in which said output detecting circuit comprises a signal delay element and an Exclusive OR gate constituting a detection circuit for detecting the level changes in the data signal read out from internal memory cells and an OR gate taking a logical OR between the output signal from said detection circuit and the output control signal, thereby detecting the level changes in the data signal and in the output control signal, both the data and output control signals inputted to the data output buffer circuit. 
     
     
       3. A semiconductor device according to claim 1, in which said output detecting circuit comprises a signal delay element and an Exclusive OR gate constituting a detection circuit for detecting the level changes in the data signal read out from internal memory cells and an AND gate taking a logical AND between the output signal from said detection circuit and the output control signal, thereby detecting the level changes in the data signal inputted to the data output buffer circuit while the output control signal is at its high level. 
     
     
       4. A semiconductor device according to claim 2 or 3, in which said detection circuit constituted by said signal delay element and said Exclusive OR gate outputs one-shot pulses in response to the level changes in the data signal. 
     
     
       5. A semiconductor device according to claim 1, in which said device includes a power supply line and a ground line, said data output buffer circuit comprising: a complementary set of first and second field effect transistors, each source of which being connected to the power supply line and the ground line, the drains of which being tied together and connected to a signal output terminal;   an inverter receiving at its input said output control signal;   a two-input NAND gate receiving at one input said data signal and at the other input said output control signal and outputting a signal to the gate of said first transistor; and   a two-input NOR gate receiving at one input said data signal and at the other input said output control signal inverted by said inverter and outputting a signal to the gate of said second transistor.   
     
     
       6. A semiconductor device according to claim 5, in which said first field effect transistor is of a P-channel depletion mode and said second field effect transistor is of an N-channel enhancement mode. 
     
     
       7. A semiconductor device according to claim 5, in which said signal input circuit is a ratio circuit comprising a complementary set of third and fourth field effect transistors, the gates of said transistors being tied together and receiving said externally applied signal, the source of said third transistor being connected to the power supply line, the source of said fourth transistor being connected to the ground line, and the drains of said transistors being tied together and outputting an output signal. 
     
     
       8. A semiconductor device according to claim 7, in which said third field effect transistor is of a P-channel depletion mode and said fourth field effect transistor is of an N-channel enhancement mode. 
     
     
       9. A semiconductor device according to claim 7, in which said holding circuit comprises: a tri-state buffer having an input, an output and an enabling signal input, said input and output being connected between the output and the input of said signal input circuit constituted by said third and fourth field effect transistors and said enabling signal input being connected to the output of said output detecting circuit;   a transfer gate circuit having a set of fifth and sixth field effect transistors, disposed between the external signal input terminal and the input of said signal input circuit, the gate of said fifth transistor connected to the output of said output detecting circuit;   an inverter, an input of which is connected to the output of said output detecting circuit and an output of which is connected to the gate of said sixth transistor.   
     
     
       10. A semiconductor device according to claim 9, in which said fifth field effect transistor is of a P-channel depletion mode and said sixth field effect transistor is of an N-channel enhancement mode. 
     
     
       11. A semiconductor device according to claim 9, in which said tri-state buffer and said third and fourth transistors constitute a flip-flop circuit.