Option/sequence selection circuit with sequence selection first

Abstract

A circuit is provided having a plurality of flip flops (F l -F n ) that are serially connected for executing sequential operations under the control of a clock. The outputs (Q l -Q n ) of the flip flops (F l -F n ) are connected to corresponding inputs (I l -I n ) of a binary decoder and the sequential outputs (O 1 -O 2 ) of the binary decoder execute the sequential selection. However, when an optional operation is selected during the execution of the sequential selection, a first switch switches the state of the clock terminals of the flip flops to a "high level" so that the flip flops memorize the state of the interrupted sequence selection. Subsequently, the option selection is carried out by the manipulation of a set of switches. Upon completion of the option selection, the first switch is switched back so that the execution of the interrupted sequence selection continues.

I claim: 
     
       1. An option/sequence selection circuit having a sequence selection first option, comprising: first switching means for switching between a first power source and ground and developing a first control signal and a first inverted control signal indicative of an option selection and a sequence selection;   combining means for performing a logical AND function between said first power source and said first control signal and developing a second control signal and a second inverted control signal;   clock means for developing a control clock pulse;   a plurality of sequentially connected stages having an input node and an output node, said control clock pulse being supplied to said input node of the first stage, each stage including, a flip flop having a clock input and an output,   a first transmission gate having a first node connected to the clock input of the flip flop, a second node connected to the output node of a preceding stage, a third node connected to the inverted control terminal and a control node connected to said control terminal,   a second transmission gate having a first node connected to the output of the flip flop, a second node for developing a second transmission gate output, a third node connected to the inverted control terminal and a control node connected to said control terminal,   a stage switch for switching between said first power source and a second power source, the common terminal of said stage switching being connected to said transmission gate output,   an OR gate connected to said transmission gate output and said input node for performing a logical OR function; and     binary decoding means for receiving said transmission gate outputs from each of said stages at a plurality of consecutive inputs which are controlled by said stage switches for each of said stages and developing a plurality of outputs from the selection circuit.