Meta-stable free flipflop

Abstract

A flipflop circuit is responsive to a clock signal for latching the terminal logic state of the input signal at an output irrespective of the relative transistions of the input data signal and the clock signal thereby providing immunity from the meta-stable condition. The input data signal is propagated from the input through a first stage to an intermediate node during a first clock cycle. A boost signal is applied at the intermediate node via first or second transistors for driving the potential developed thereat toward the terminal logic state of the input data signal. The logic state stored at the intermediate node may be used as the output signal or passed through additional buffer stages to an output during subsequent cycles of the clock signal.

I claim: 
     
       1. A flipflop circuit responsive to a clock signal for latching at an output an input data signal applied at an input, comprising: circuit means coupled between the input and the output for propagating the input signal applied at the input, the circuit means having an intermediate node wherein the input data signal is propagated through to said intermediate node during a first portion of the clock signal and passed through to the output during a second portion of the clock signal;   a first transistor having a gate, a drain and a source, said gate being coupled for receiving the inverse state of the input data signal, said source being coupled to a first source of operating potential, said drain being coupled to said intermediate node; and   a second transistor having a gate, a drain and a source, said gate being coupled for receiving the inverse state of the input data signal, said source being coupled to a second source of operating potential, said drain being coupled to said intermediate node.   
     
     
       2. The flipflop circuit of claim 1 further including a first inverter coupled between the input and said gate of said first transistor. 
     
     
       3. The flipflop circuit of claim 2 further including a second inverter coupled between the input and said second transistor. 
     
     
       4. The flipflop circuit of claim 3 wherein said circuit means includes: a third inverter having an input coupled to the input of the flipflop circuit and having an output;   a first transmission gate having an input, an output and first and second control inputs, said input being coupled to said output of said third inverter, said first control input being coupled for receiving the inverse of the clock signal, said second control input being coupled for receiving the clock signal;   a fourth inverter having an input coupled to said output of said first transmission gate and having and output coupled to said intermediate node;   a fifth inverter having an input coupled to said output of said fourth inverter and having an output; and   a second transmission gate having an input, an output and first and second control inputs, said input being coupled to said output of said fifth inverter, said output being coupled to said input of said fourth inverter, said first control input being coupled for receiving the clock signal, said second control input being coupled for receiving the inverse of the clock signal.   
     
     
       5. The flipflop circuit of claim 4 wherein said circuit means further includes: a third transmission gate having an input, an output and first and second control inputs, and input being coupled to said intermediate node, said first control input being coupled for receiving the clock signal, said second control input being coupled for receiving the inverse of the clock signal;   a sixth inverter having an input coupled to said output of said third transmission gat and having an output;   a seventh inverter having an input coupled to said output of said sixth inverter and having an output coupled to the output of the flipflop circuit;   an eighth inverter having an input coupled to said output of said sixth inverter and having an output; and   a fourth transmission gate having an input, an output and first and second control inputs, said input being coupled to said output of said eighth inverter, said output being coupled to said input of said sixth inverter, said first control input being coupled for receiving the inverse of the clock signal, said second control input being coupled for receiving the clock signal.   
     
     
       6. The flipflop circuit of claim 5 wherein said first transmission gate includes: a third transistor having a gate, a drain and a source, said gate being coupled to said first control input of said first transmission gate, said drain being coupled to said input, said source being coupled to said output; and   a fourth transistor having a gate, a drain and a source, said gate being coupled to said second control input of said first transmission gate, said drain being coupled to said input, said source being coupled to said output.   
     
     
       7. A circuit for latching an input data signal at an output in response to a clock signal including a circuit means coupled between the input and the output for propagating the input signal therebetween, the circuit means having an intermediate node wherein the input data signal is propagated through to said intermediate node during a first portion of the clock signal and passed through to the output during a second portion of the clock signal, wherein the improvement comprises: a first transistor having a gate, a drain and a source, said source being coupled to a first source of operating potential, said drain being coupled to said intermediate node;   a first inverter coupled between the input and said gate of said first transistor;   a second transistor having a gate, a drain and a source, said source being coupled to a second source of operating potential, said drain being coupled to said intermediate node; and   a second inverter coupled between the input and said gate of said second transistor.   
     
     
       8. The flipflop circuit of claim 7 wherein the circuit means includes: a third inverter having an input coupled to the input of the flipflop circuit and having an output;   a first transmission gate having an input, an output and first and second controls inputs, said input being coupled to said output of said third inverter, said first control input being coupled for receiving the inverse of the clock signal, said second control input being coupled for receiving the clock signal;   a fourth inverter having an input coupled to said output of said first transmission gate and having an output coupled to said intermediate node;   a fifth inverter having an input coupled to said output of said fourth inverter and having an output; and   a second transmission gate having an input, an output and first and second control inputs, said input being coupled to said output of said fifth inverter, said output being coupled to said input of said fourth inverter, said first control input being coupled for receiving the clock signal, said second control input being coupled for receiving the inverse of the clock signal.   
     
     
       9. The flipflop circuit of claim 8 wherein the circuit means further includes: a third transmission gate having an input, an output and first and second control inputs, said input being coupled to said intermediate node, said first control input being coupled for receiving the clock signal, said second control input being coupled for receiving the inverse of the clock signal;   a sixth inverter having an input coupled to said output of said third transmission gate and having an output;   a seventh inverter having an input coupled to said output of said sixth inverter and having an output coupled to the output of the flipflop circuit;   an eighth inverter having an input coupled to said output of said sixth inverter and having an output; and   a fourth transmission gate having an input, an output and first and second control inputs, said input being coupled to said output of said eighth inverter, said output being coupled to said input of said sixth inverter, said first control input being coupled for receiving the inverse of the clock signal, said second control input being coupled for receiving the clock signal.   
     
     
       10. The flipflop circuit of claim 9 wherein said first transmission gate includes: a third transistor having a gate, a drain and a source, said gate being coupled to said first control input of said first transmission gate, said drain being coupled to said input, said source being coupled to said output; and   a fourth transistor having a gate, a drain and a source, said gate being coupled to said second control input of said first transmission gate, said drain being coupled to said input, said source being coupled to said output.   
     
     
       11. A method of providing a known logic state for the output signal of a flipflop circuit when the input data signal changes state at the edge of an applied clock signal, comprising the steps of: propagating the input data signal from the input to an intermediate node during a first portion of the clock signal; and   applying a boost signal for driving the signal stored at said intermediate node to the terminal logic state of the input data signal.   
     
     
       12. The method of claim 11 further comprising the step of passing the logic state stores at the intermediate node to the output during a second portion of the clock signal. 
     
     
       13. The method of claim 12 wherein the step of propagating the input data signal includes the steps of: inverting the input data signal:   sampling the inverted input data signal; and   inverting the inverted input data signal and storing the signal level thereof at said intermediate node.   
     
     
       14. The method of claim 13 wherein the step of applying a boost signal includes the steps of: inverting the input data signal: and   enabling a transistor coupled between a source of operating potential and said intermediate node for charging the logic state thereof toward the terminal logic state of the input data signal.   
     
     
       15. A flipflop circuit responsive to a clock signal for latching at an output an input data signal applied at an input, comprising: circuit means coupled between the input and the output for propagating the input signal therebetween, wherein the input data signal is propagated through to the output during a first portion of the clock signal;   a first transistor having a gate, a drain and a source, said gate being coupled for receiving the inverse state of the input data signal, said source being coupled to a first source of operating potential, said drain being coupled to the output; and   a second transistor having a gate, a drain and a source, said gate being coupled for receiving the inverse state of the input data signal, said source being coupled to a second source of operating potential, said drain being coupled to the output.   
     
     
       16. The flipflop circuit of claim 15 further including a first inverter coupled between the input and said gate of said first transistor. 
     
     
       17. The flipflop circuit of claim 16 further including a second inverter coupled between the input and said gate of said second transistor. 
     
     
       18. The flipflop circuit of claim 17 wherein said circuit means includes: a third inverter having an input coupled to the input of the flipflop circuit and having an output;   a first transmission gate having an input, an output and first and second control inputs, said input being coupled to said output of said third inverter, said first control input being coupled for receiving the inverse of the clock signal, said second control input being coupled for receiving the clock signal;   a fourth inverter having an input coupled to said output of said first transmission gate and having an output coupled to the output of the flipflop circuit;   a fifth inverter having an input coupled to said output of said fourth inverter and having an output; and   a second transmission gate having an input, an output and first and second control inputs, said input being coupled to said output of said fifth inverter, said output being coupled to said input of said fourth inverter, said first control input being coupled for receiving the clock signal, said second control input being coupled for receiving the inverse of the clock signal.