Digital signal direction detection circuit

Abstract

A digital circuit includes two digital signal sources, each having an output terminal connected to corresponding bus portions. Logic connects the two bus portions for propagating a signal pulse on one of the bus portions onto the other of the bus portion, and produces a digital indication signal signifying which of the signal sources generated the signal pulse. The logic includes logic gates, each having a first input connected to its corresponding bus portion, an output terminal connected to the indicator output, and a second input terminal connected to the output terminal of the opposite logic gate. The output of each logic gate also controls the connection of the other bus portion to a voltage source to bring that bus portion to the active state in response to the other bus portion being rendered active by its associated signal source.

I claim: 
     
       1. A digital circuit comprising: first and second digital signal sources, each having an output terminal;   a first bus portion connected to the output terminal of said first signal source;   a second bus portion connected to the output terminal of said second signal source;   digital logic connecting said first and second bus portions for propagating a signal pulse on one of said bus portions onto the other of said bus portions, and for producing an indication signal signifying which of said signal sources generated the signal pulse, wherein said digital logic comprises: a first logic gate having first and second input terminals and an output terminal, wherein said first input terminal is connected to said first bus portion;   a second logic gate having first and second input terminals and an output terminal, wherein said first input terminal is connected to said second bus portion, said second input terminal is connected to said output terminal of said first logic gate, and said output terminal of said second logic gate is connected to said second input terminal of said first logic gate;   a first indicator output terminal connected to said output terminal of said first logic gate;   a second indicator output terminal connected to said output terminal of said second logic gate;     a first voltage source connected to said first and second bus portions;   a second voltage source;   a first switch for selectively connecting said second voltage source to said first bus portion; and   a second switch for selectively connecting said second voltage source to said second bus portion;   wherein:   said output terminal of said first logic gate is connected to said second switch to control said second switch; and   said output terminal of said second logic gate is connected to said first switch to control said first switch.   
     
     
       2. A digital signal direction detection circuit comprising: a first circuit input terminal;   a second circuit input terminal;   a first logic gate having a first input terminal, a second input terminal, and an output terminal;   a second logic gate having a first input terminal, a second input terminal, and an output terminal;   wherein:   said output terminal of said first logic gate is connected to a first indication line;   said output terminal of said second logic gate is connected to a second indication line;   said first input terminal of said first logic gate is connected to said first circuit input terminal, to a first voltage source, and, through a first FET switch, to a second voltage source;   said first input terminal of said second logic gate is connected to said second circuit input terminal, to said first voltage source, and, through a second FET switch, to said second voltage source;   said second input terminal of said first logic gate is connected to the gate of said first FET switch and to said output terminal of said second logic gate; and   said second input terminal of said second logic gate is connected to the gate of said second FET switch and to said output terminal of said first logic gate.   
     
     
       3. The digital signal direction detection circuit of claim 2, wherein: said first and second logic gates are NOR gates;   said first voltage source is at approximately +5 volts;   said second voltage source is at approximately ground potential; and   said first and second FET switches are enhancement-mode FETs.   
     
     
       4. The digital signal direction detection circuit of claim 2, wherein: said first and second logic gates are NAND gates;   said first voltage source is at approximately ground potential;   said second voltage source is at approximately +5 volts; and   said first and second FET switches are depletion-mode FETs.   
     
     
       5. A digital signal direction detection circuit comprising: a first circuit input terminal;   a second circuit input terminal;   a first logic gate having a first input terminal connected to said first circuit input terminal, a second input terminal, and an output terminal;   a second logic gate having a first input terminal connected to said second circuit input terminal, a second input terminal connected to said output terminal of said first logic gate, and an output terminal connected to said second input terminal of said first logic gate;   a first source of a first electric potential connected to said first and second circuit input terminals;   a second source of a second electric potential;   a first switch connected between said second electric potential source and said first circuit input terminal and having a control terminal connected to said output terminal of said second logic gate for selectively connecting said second electric potential source and said first circuit input terminal; and   a second switch connected between said second electric potential source and said second circuit input terminal and having a control terminal connected to said output terminal of said first logic gate for selectively connecting said second electric potential source and said second circuit input terminal.   
     
     
       6. The circuit of claim 5 wherein: said first switch is an FET having its conduction path connected between said second source of electric potential and said first circuit input terminal, and having its gate connected to said output terminal of said second logic gate; and   said second switch is an FET having its conduction path connected between said second source of electric potential and said second circuit input terminal and having its gate connected to said output terminal of said first logic gate.   
     
     
       7. The circuit of claim 6, wherein: said first and second logic gates are NOR gates;   said first source of electric potential is a source of relatively high electric potential; and   said second source of electric potential is a source of relatively low electric potential.   
     
     
       8. The circuit of claim 6, wherein: said first and second logic gates are NAND gates;   said first source of electric potential is a source of relatively low electric potential; and   said second source of electric potential is a source of relatively high electric potential.   
     
     
       9. The circuit of claim 6, wherein: said first switch is an FET having its conduction path connected between said second source of electric potential and said first circuit input terminal, and having its gate connected to said output terminal of said second logic gate; and   said second switch is an FET having its conduction path connected between said second source of electric potential and said second circuit input terminal and having its gate connected to said output terminal of said first logic gate.   
     
     
       10. The circuit of claim 9, wherein: said first and second logic gates are NOR gates;   said first voltage source is a source of relatively high electric potential; and   said second voltage source is a source of relatively low electric potential.   
     
     
       11. The circuit of claim 9, wherein: said first and second logic gates are NAND gates;   said first voltage source is a source of relatively low electric potential; and   said second voltage source is a source of relatively high electric potential.