Step adjustable distributed amplifier network structure
Abstract
The requirements of extreme miniaturization, remote operation, wide bandwidth, good reproducibility in high quantities, low cost and low insertion loss are met with an incrementally adjustable distributed network arrangement in the general configuration of a distributed amplifier. The arrangement comprises delay elements (Z Dm , Z Gm ) and a plurality of controlled sources (T n-2 , T n-1 , T ni VCCS), a signal input (E) and a signal output (A). The controlled sources (T n-2 , T n-1 , T ni VCCS) may be selectively turned on and off. Dual gate FETs (T 1 , . . . T n ) are employed as controlled sources, whose first gate (G 1 ) is connected to the input signal voltage through delay elements (Z Gm ) and whose second gate (G 2 ) is maintained at suitable dc voltages for turning the respective FETs on and off.
Claims
exact text as granted — not AI-modifiedI claim:
1. An incrementally adjustable distributed network arrangement including a signal delay line connected to an input signal (E) and an output delay line providing a signal output (A), the arrangement comprising delay elements (Z Gm , Z Dm , mε {1, . . . , n+1}) and a number of controlled sources (T 1 . . . T n ; VCCS), connected together to form a distributed amplifier responsive to a signal input (E) and providing a signal output (A), the distributed amplifier comprising: (a) the number of controlled sources (VCCS) being selected to produce a predetermined level of amplification and each controlled source being individually switched to turn-on or turn-off; (b) a plurality of dual gate FETs (T 1 . . . T n ) comprising said controlled sources, each dual gate FET having a first gate (G 1 ) for receiving the input signal voltage through serially connected delay elements (Z Gm ) forming the input signal delay line, and each dual gate FET having a second gate respectively connected to receive a suitable dc voltage for turning its respective FET on and off; and (c) the dual gate FETs (T 1 . . . T n ) being series connected, the respective first gates of the dual gate FETs (T 1 . . . T n ) being coupled to the input signal delay line of the distributed amplifier, the respective drains of the dual gate FETs (T 1 . . . T n ) being coupled to the output delay line formed by serially connected delay line elements of the distributed amplifier, the respective sources of the dual gate FETs (T 1 . . . T n ) being coupled to a fixed potential, delay elements being coupled between gates of succeeding dual gate FETs and between drains of succeeding dual gate FETs, respectively, the output delay line as well as the signal delay line being respectively terminated with a resistance; and a system of second FETs wherein individual second FETs being disposed in parallel with a corresponding controlled source to form a parallel connected FET in order to avoid impedance transitions during the turning on and off of one or more controlled sources (VCCS), each individual second FET having a first gate (G 1 ) that is connected to a fixed potential and a second gate (G m ) that is at a switching voltage at which no current flows in the system of second FETs with the parallel connected FET, when applied signal voltage input, is active, and that this second FET system is active when there is no current flow in the parallel connected FET transistor that is provided with signal voltage.
2. An incrementally adjustable distributed network arrangement according to claim 1, wherein the controlled sources each have a transconductance in a prescribed proportional relationship to each other to provide equal increments of amplification for the distributed amplifier corresponding to the turn-on and turn-off of each additional source.
3. An incrementally adjustable distributed network arrangement according to claim 1, wherein the individual dual gate FETs each have a transconductance forming a preselected proportional relationship providing steps in amplification and the FETs T 1 , T 2 , . . . T n being serially connected to continually increase or decrease the amplification.
4. An incrementally adjustable distributed network arrangement according to claim 1, wherein the number of controlled sources is at least as great as incremental steps in amplification desired.
5. An incrementally adjustable distributed network arrangement according to claim 1, wherein the controlled sources comprise DG-FETs having transconductances in preselected proportional relationship to each other so that maximum amplification is achieved, upon turning on all the sources.
6. An incrementally adjustable distributed network arrangement according to claim 1, wherein the number of controlled sources may be selectively turned on or off individually corresponding to a preselected difference in amplification.
7. An incrementally adjustable distributed network arrangement according to claim 1, wherein the FETs of the system of second FETs each comprise parallel connected FETs having a common source zone and a common drain zone.
8. An incrementally adjustable distributed network arrangement according to claim 7, wherein the number of controlled sources may selectively be turned on or off individually corresponding to a preselected difference in amplification.
9. An incrementally adjustable distributed network arrangement according to claim 7, wherein the controlled sources comprise DG-FETs having transconductances in preselected proportional relationship to each other so that maximum amplification is achieved, upon turning on all the sources.
10. An incrementally adjustable distributed network arrangement according to claim 7, wherein the number of controlled sources at least corresponds to a number of levels in amplification.
11. An incrementally adjustable distributed network arrangement according to claim 10, wherein the controlled sources comprise DG-FETs having transconductances in preselected proportional relationship to each other so that maximum amplification is achieved, upon turning on all the sources.
12. An incrementally adjustable distributed network arrangement according to claim 7, wherein the controlled sources have individual transconductances of selected values relative to each other that, the turn-on and turn-off of each additional source results in equal increments of amplification.
13. An incrementally adjustable distributed network arrangement according to claim 12, wherein the number of controlled sources is at least as great as a number of the levels in amplification desired.
14. An incrementally adjustable distributed network arrangement according to claim 12, wherein the controlled sources comprise DG-FETs having transconductances in preselected proportional relationship to each other so that maximum amplification is achieved, upon turning on all the sources.
15. An incrementally adjustable distributed network arrangement according to claim 12, wherein the number of controlled sources may selectively be turned on or off individually corresponding to a preselected difference in amplification.
16. An incrementally adjustable distributed network arrangement according to claim 7, wherein the individual FETs of the plurality each have a transconductance forming a preselected proportional relationship to provide steps in amplification and the FETs T 1 , T 2 , . . . T n being serially connected to increase or decrease the amplification in a prescribed manner.
17. An incrementally adjustable distributed network arrangement according to claim 16, wherein the controlled sources comprise DG-FETs having transconductances in preselected proportional relationship to each other so that maximum amplification is achieved, upon turning on all the sources.
18. An incrementally adjustable distributed network arrangement according to claim 16, wherein the number of controlled sources at least corresponds to incremental steps in amplification.
19. An incrementally adjustable distributed network arrangement according to claim 14, wherein the number of controlled sources may selectively be turned on or off individually corresponding to a preselected difference in amplification.Join the waitlist — get patent alerts
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