Semiconductor device

Abstract

A semiconductor device comprises a semiconductor chip having main power supply lines which are arranged in peripheral regions in the vicinity of edges of the semiconductor chip and which are formed with multi-level metallization. The main power supply lines are formed with arrangements in that layers of the same potential face each other through an insulating layer in chip corner regions adjacent to corners of the semiconductor chip.

What is claimed is: 
     
       1. A semiconductor device comprising: a semiconductor chip having main power supply lines which are arranged in peripheral regions in the vicinity of edges of said semiconductor chip, said main power lines being formed with multi-level layers with a first insulating layer being interposed therebetween, said multi-level layers being formed on a second insulating layer provided on said semiconductor chip, each of said main power lines being formed with arrangements in that layers of the same potential face each other through said first insulating layer in chip corner regions adjacent to corners of said semiconductor chip; and a package made of plastics for sealing said semiconductor chip.   
     
     
       2. A semiconductor device as claimed in claim 1, wherein said layers of the same potential in said chip corner regions are electrically connected by means of metallic material which is filled into through holes formed in said insulating layer which is sandwiched between said layers of the same potential. 
     
     
       3. A semiconductor device as claimed in claim 1, wherein said layers of the same potential formed in said chip corner regions is narrower than other parts thereof in regions other than said chip corner regions. 
     
     
       4. A semiconductor device as claimed in claim 1, wherein in regions other than said chip corner regions, said main power lines are fomred with arrangements in that layers of different potential face each other through said insulating layer. 
     
     
       5. A semiconductor device as claimed in claim 1, wherein said main power supply lines are formed to be concentric in peripheral regions in the vicinity of edges of said semiconductor chip. 
     
     
       6. A semiconductor device comprising: a semiconductor chip sealed by a plastic material and having an intergrated circuit region and corner regions;   a first main power supply line formed on said semiconductor chip and surrounding the intergrated circuit region, for supplying a first power source voltage to the integrated circuit region;   an insulating layer for insulating said first main power supply line; and   a second main power supply line formed on said semiconductor chip, for supplying a second power source voltage to said integrated circuit region, said second main power supply line being overlapped with said first main power supply line via said insulating layer in regions other than the corner regions and unoverlapped in said corner regions, and each of said first and second main power supply lines having a multi layer wiring structure in the corner regions.   
     
     
       7. A semiconductor device as claimed in claim 6, wherein said first and second main power supply lines have first width in the regions other than the corner regions and second width in the corner regions, which is smaller than the first width. 
     
     
       8. A semiconductor device as claimed in claim 7, wherein said second width is smaller than a half of the first width. 
     
     
       9. A semiconductor device comprising: a semiconductor chip, sealed by a plastic material, having an intergrated circuit, first, second, third and fourth edges, and first, second, third and fourth corners;   a first wiring layer formed on said semiconductor chip;   an insulating layer formed on said first wiring layer;   a second wiring layer formed on said insulating layer; and   first and second main power supply lines formed by said first and second wiring layers and arranged along the first, second, third and fourth edges for supplying power source voltages to the integrated circuit, said first and second main power supply lines being overlapped each other in regions other than said first, second, third and fourth corners.   
     
     
       10. A semiconductor device as claimed in claim 9, wherein said first main power supply line comprises a first portion formed by said first wiring layer and a second portion formed by second wiring layer at the first to fourth corners; and said second main power supply line comprises a first portion formed by said second wiring layer and a second portion formed by said first wiring layer at the first to fourth edges. 
     
     
       11. A semiconductor device as claimed in claim 9, wherein said first main power supply line comprises first and third portion formed by said first wiring layer and arranged along the first and second edges respectively, and second fourth portion formed by said second wiring layer and arranged along the second and fourth edges respectively, and each of the portions are connected each other at the first to fourth corners; and said second main power supply line comprises first and third portion formed by said second wiring layer and arranged along the first and second edges respectively; and second and fourth portion formed by said first wiring layer and arranged along the second and fourth edges respectively, and each of the portions are connected each other at the first to fourth corners.