Serial access memory circuit with improved serial addressing circuit composed of a shift register

Abstract

A serial access memory circuit provided with an improved serial addressing circuit which can be fabricated with a reduced number of elements, is disclosed. The memory circuit comprises a memory array of N columns to be serially accessed, and a serial selection circuit including a shift register of N/K stages, a control circuit generating K output signals and a gate circuit receiving output signals of N/K stages of the shift register and K output signals of the control circuit and generating N output signals.

I claim: 
     
       1. A memory circuit comprising a memory array of memory cells having N addresses, wherein N is a positive integer larger than 3, to be serially selected, and a serial selection circuit for serially selecting said N addresses one by one in synchronism with control pulses, said serial selection circuit including a shift register having N/K, wherein K is a positive integer equal or larger than 2 and less than N, shift outputs, said shift register activating sequentially the N/K shift outputs sequentially one by one in synchronism with said control pulses, a control circuit having K control outputs and activating only one of the K control outputs, said control circuit changing the output from one of said K control outputs to another after said shift register activates all the N/K shift outputs, and a gate circuit coupled to said N/K shift outputs of said shift register and to said K control outputs of said control circuit and generating N selection output signals one by one. 
     
     
       2. The memory circuit according to claim 1, in which said gate circuit includes N/K gate unit circuits, each of said gate unit circuits being coupled to one of said N/K shift outputs and to said K control outputs and having K selection outputs. 
     
     
       3. The memory circuit according to claim 1, in which said shift register includes N/K stages of D-type flip-flop connected in cascade. 
     
     
       4. A memory circuit comprising a memory array having a plurality of memory cells arranged in rows and N columns wherein N is an integer larger than 3, and a serial selection circuit for serially selecting said N columns one column by one column in response to control pulses, said serial selection circuit including a shift register having N/K shift stages, wherein K is an integer equal or larger than 2 and less than N, and generating output signals one stage by one stage in synchronism with said control pulses through said shift stages, a state control circuit having K control outputs, one of said K control outputs being activated and the location of the activated control output being changed when all the N/K shift stages of said shift register have generated output signals a gate circuit having N/K gate units and N output signals, each of said gate units being coupled to said K control outputs and receiving one of said output signals of said N/K shift stages, and a selection circuit responsive to the N outputs signals of said gate circuit for selecting one of said N columns. 
     
     
       5. The memory circuit of claim 4, in which each of N/K gate units of said gate circuit has K AND-gates, each of said K AND-gate having two inputs and one output, one of said two inputs being coupled to one of said K control outputs and the other of said two inputs receiving in common said one of output signals of said N/K shift stages.