Power supply voltage level sensing circuit

Abstract

A power supply voltage level sensing circuit on an integrated circuit generates a reset signal that holds the components of the integrated circuit in a defined state when the power supply voltage level drops below a predetermined voltage. The reset signal is released when the power supply voltage level returns to above the predetermined voltage. The voltage level sensing circuit is comprised of two inverters and a filter circuit. The inverters start to conduct at different power supply voltage levels and have different trigger point characteristics. The power supply voltage level sensing circuit may be coupled with a power-on reset circuit to create a voltage sensing power-on reset circuit which generates a reset signal not only when the power supply voltage is first supplied to the circuit, but also when the power supply voltage level temporarily falls below a selected value.

I claim: 
     
       1. A semiconductor device having a power supply voltage level sensing circuit comprising: first means, having a power supply terminal and an output terminal, for providing a first output signal in response to the power supply voltage rising above a first selected value;   second means for receiving said first output signal and for providing a second output signal in response to the power supply voltage rising above a second selected value wherein;   said second output signal has a level greater than the level of said first output signal if said power supply voltage is greater than a third selected value and said second output signal has a level less than said level of said first output signal if said power supply voltage is less than said third selected value;   filter means, having an input terminal and an output terminal, for receiving said second output signal and generating a third output signal having a first value ifs aid second output signal has a first selected value and if said second output signal has a second selected value for less than a selected period of time, and having a second value if said second output signal has a second selected value for greater than said selected period of time.   
     
     
       2. A semiconductor device having a power supply voltage level sensing circuit as in claim 1 wherein said first means comprises: a first transistor having a first drain/source connected to said power supply terminal, a gate connected to a reference voltage, and a second drain/source;   a second transistor having a first drain/source connected to said second drain/source of said first transistor, a second drain/source connected to said output terminal and a gate connected to said output terminal;   a third transistor having a first drain/source connected to said output terminal, a gate connected to said output terminal, and a second drain/source; and   a fourth transistor having a first drain/source connected to said second drain/source of said third transistor, a gate connected to said first drain/source of said fourth transistor and a second drain/source connected to said reference voltage.   
     
     
       3. A semiconductor device having a power supply voltage level sensing circuit as in claim 2 wherein said first transistor and said second transistor are P channel enhancement mode transistors and said third transistor and said fourth transistor are N channel enhancement mode transistors. 
     
     
       4. A semiconductor device having a power supply voltage level sensing circuit as in claim 3 wherein said first selected value is determined by the threshold voltage of said first and said second P channel enhancement mode transistors. 
     
     
       5. A semiconductor device having a power supply voltage level sensing circuit as in claim 3 wherein said third selected value is determined by the ratio of the width to length ratio of said third transistor to the width to length ratio of said second transistor. 
     
     
       6. A semiconductor device having a power supply voltage level sensing circuit as in claim 5 wherein said ratio of the width to length ratio of said third transistor to the width to length ratio of said second transistor is greater than 100. 
     
     
       7. A semiconductor device having a power supply voltage level sensing circuit as in claim 1, further comprising means for turning off said first means and for providing a selected input signal to said second means. 
     
     
       8. A semiconductor device having a power supply voltage level sensing circuit as in claim 7 wherein said first means comprises: a first transistor having a first drain/source connected to said power supply terminal, a gate connected to a first conductor, and a second drain/source;   a second transistor having a first drain/source connected to said second drain/source of said first transistor, a gate connected to said output terminal, and a second drain/source connected to said output terminal;   a third transistor having a first drain/source connected to said output terminal, a gate connected to said output terminal, and a second drain/source; and   a fourth transistor having a first drain/source connected to said second drain/source of said third transistor, a gate connected to said first drain/source of said fourth transistor and a second drain/source connected to a reference voltage.   
     
     
       9. A semiconductor device having a power supply voltage level sensing circuit as in claim 8 wherein said means for turning off said first means and for providing said input signal to said second means comprises said first conductor and a fifth transistor, said fifth transistor having a first drain/source connected to said output terminal of said first means, a second drain/source connected to said reference voltage and a gate connected to said first conductor wherein when a selected voltage is applied to said first conductor, said first transistor of said first means is turned off and said fifth transistor is turned on.   
     
     
       10. A semiconductor device having a power supply voltage level sensing circuit as in claim 9 wherein said first transistor and said second transistor are P channel enhancement mode transistors and said third transistor, said fourth transistor, and said fifth transistor are N channel enhancement mode transistors. 
     
     
       11. A semiconductor device having a power supply voltage level sensing circuit as in claim 10 wherein said first selected value is determined by the threshold voltage of said first and said second P channel enhancement mode transistors. 
     
     
       12. A semiconductor device having a power supply voltage level sensing circuit as in claim 10 wherein said third selected value is determined by the ratio of the width to length ratio of said third transistor to the width to length ratio of said second transistor. 
     
     
       13. A semiconductor device having a power supply voltage level sensing circuit as in claim 12 wherein said ratio of the width to length ratio of said third transistor to the width to length ratio of said second transistor is greater than 100. 
     
     
       14. A semiconductor device as in claim 1 wherein said filter means comprises: an inverter which receives said second output signal and provides the complement of said second output signal;   a NAND gate having a first input terminal, a second input terminal and an output terminal, said output terminal providing said third output signal;   a conductor which provides said complement of said second output signal to said first input terminal of said NAND gate;   a delay circuit having an input terminal, an output terminal and a time constant equal to said selected period of time, wherein said input lead of said delay circuit receives said complement of said second output signal and after said selected period of time provides said complement of said second output signal to said second input terminal of said NAND gate;   whereby said NAND gate provides a logical zero output signal as said third output signal only if said second output signal remains a logical zero continuously for at least said selected period of time.   
     
     
       15. A semiconductor device having a power supply voltage level sensing circuit as in claim 14 wherein said second means comprises a first CMOS inverter and said inverter of said filter means comprises a second CMOS inverter, each of said CMOS inverters having an input lead and an output lead wherein: said input lead of said first CMOS inverter receives said first output signal;   said output lead of said first CMOS inverter is tied to said input lead of said second CMOS inverter; and   said complement of said second output signal is provided on said output lead of said second CMOS inverter.   
     
     
       16. A semiconductor device having a power supply voltage level sensing circuit as in claim 15 wherein: each of said CMOS inverters comprises an unimplanted P channel enhancement mode transistor and an N channel enhancement mode transistor; and   said second selected value is the threshold voltage of said unimplanted P channel enhancement mode transistor of said first inverter.   
     
     
       17. A semiconductor device having a power supply voltage level sensing circuit as in claim 1 wherein said filter means comprises: a conductor having a first end connected to said input terminal of said filter means;   a logic gate having a first input terminal, a second input terminal and an output terminal wherein a second end of said conductor is connected to said first input terminal of said logic gate and said output terminal of said logic gate is said output terminal of said filter means;   a delay circuit having an input lead, an output lead and a time constant, wherein said input lead of said delay circuit is connected to said input terminal of said filter means and said output lead of said delay circuit is connected to said second input terminal of said logic gate; and further wherein   said time constant of said delay circuit is said selected time period.   
     
     
       18. A semiconductor device having a power supply voltage level sensing circuit as in claim 17 wherein said delay circuit comprises: a first CMOS inverter having an input terminal and an output terminal, said input terminal of said first CMOS inverter being connected to said input lead of said delay circuit;   a resistive means having a first lead and a second lead, said first lead being connected to said output terminal of said first CMOS inverter;   a first capacitive means having a first plate and a second plate, said first plate being connected to said second lead of said resistive means and said second plate being connected to a reference voltage;   a second CMOS inverter having an input terminal and an output terminal, said input terminal being connected to said first plate of said first capacitive means; and   a second capacitive means having a first plate and a second plate, said first plate being connected to said power supply voltage and said second plate being connected to said output terminal of said second CMOS inverter and to said output lead of said delay circuit.   
     
     
       19. A semiconductor device having a power supply voltage level sensing circuit as in claim 18 wherein said first CMOS inverter comprises a P channel enhancement mode transistor and an N channel enhancement mode transistor;   said second CMOS inverter comprises an unimplanted P channel enhancement mode transistor and a N channel enhancement mode transistor; and   said resistive means comprises an N channel enhancement mode transistor having a first drain/source connected to said first lead of said resistive means, a second drain/source connected to said second lead of said resistive means and a gate connected to said power supply voltage.   
     
     
       20. A semiconductor device having a power supply voltage level sensing circuit as in claim 18 wherein said first CMOS inverter and said second CMOS inverter each comprise a P channel enhancement mode transistor and an N channel enhancement mode transistor; and   said resistive means comprises a transmission gate having an input terminal and an output terminal wherein said input terminal of said transmission gate is connected to said first lead of said resistive means and said output terminal of said transmission gate is connected to said second lead of said resistive means.   
     
     
       21. A reset circuit comprising: a power-on reset circuit having a power supply terminal for receiving a power supply voltage and an output terminal wherein said power-on reset circuit provides a first output signal on said output terminal in response to said power supply voltage rising above a first selected value and a second output signal complementary to said first output signal a first selected time period after said first output signal is provided;   a power supply voltage level sensing circuit having an output terminal, said power supply voltage level sensing circuit comprising: first means, having a power supply terminal and an output terminal for providing a third output signal in response to said power supply voltage rising above a second selected value;   second means for receiving said third output signal and for providing a fourth output signal in response to said power supply voltage rising above a third selected value; wherein   said fourth output signal has a level greater than the level of said third output signal if said power supply voltage is greater than a fourth selected value and said fourth output signal has a level less than said level of said third output signal if said power supply voltage is less than said fourth selected value;   filter means, having an input terminal for receiving said fourth output signal and an output terminal for providing a fifth output signal having a first value if said fourth output signal has a first selected value and if said fourth output signal has a second selected value for less than a second selected period of time, and having a second value if said fourth output signal has a second selected value for greater than said second selected period of time; and     a logic gate having a first input terminal connected to said output terminal of said power-on reset circuit, a second input terminal connected to said output terminal of said filter means and an output terminal providing an output signal from said reset circuit.   
     
     
       22. A reset circuit as in claim 21 wherein said first means comprises: a first transistor having a first drain/source connected to said power supply terminal, a gate connected to a reference voltage, and a second drain/source;   a second transistor having a first drain/source connected to said second drain/source of said first transistor, a gate connected to said output terminal, and a second drain/source connected to said output terminal; and   a third transistor having a first drain/source connected to said output terminal, a gate connected to said output terminal, and a second drain/source; and   a fourth transistor having a first drain/source connected to said second drain/source of said third transistor, a gate connected to said first drain/source of said fourth transistor and a second drain/source connected to said reference voltage.   
     
     
       23. A reset circuit as in claim 22 wherein said first transistor and said second transistor are P channel enhancement mode transistors and said third transistor and said fourth transistor are N channel enhancement mode transistors. 
     
     
       24. A reset circuit as in claim 23 wherein said second selected value is determined by the threshold voltage of said first and said second P channel enhancement mode transistors. 
     
     
       25. A reset circuit as in claim 23 wherein said fourth selected value is determined by the ratio of the width to length ratio of said third transistor to the width to length ratio of said second transistor. 
     
     
       26. A reset circuit as in claim 25 wherein said ratio of the width to length ratio of said third transistor to the width to length ratio of said second transistor is greater than 100. 
     
     
       27. A reset circuit as in claim 21, further comprising means for turning off said first means and for providing an input signal to said second means. 
     
     
       28. A reset circuit as in claim 27 wherein said first means comprises: a first transistor having a first drain/source connected to said power supply terminal, a gate connected to a first conductor, and a second drain/source;   a second transistor having a first drain/source connected to said second drain/source of said first transistor, a gate connected to said output terminal, and   a second drain/source connected to said output terminal;   a third transistor having a first drain/source connected to said output terminal, a gate connected to said output terminal, and a second drain/source; and   a fourth transistor having a first drain/source connected to said second drain/source of said third transistor, a gate connected to said first drain/source of said fourth transistor and a second drain/source connected to a reference voltage.   
     
     
       29. A reset circuit as in claim 28 wherein said means for turning off said first means and for providing said input signal to said second means comprises said first conductor and a fifth transistor, said fifth transistor having a first drain/source connected to said output terminal of said first means, a second drain/source connected to said reference voltage and a gate connected to said first conductor wherein when a selected voltage is applied to said first conductor, said first transistor of said first means is turned off and said fifth transistor is turned on.   
     
     
       30. A reset circuit as in claim 29 wherein said first transistor and said second transistor are P channel enhancement mode transistors and said third transistor, said fourth transistor, and said fifth transistor are N channel enhancement mode transistors. 
     
     
       31. A reset circuit as in claim 30 wherein said second selected value is determined by the threshold voltage of said first and said second P channel enhancement mode transistors. 
     
     
       32. A reset circuit as in claim 30 wherein said fourth selected value is determined by the ratio of the width to length ratio of said third transistor to the width to length ratio of said second transistor. 
     
     
       33. A reset circuit as in claim 32 wherein said ratio of the width to length ratio of said third transistor to the width to length ratio of said second transistor is greater than 100. 
     
     
       34. A reset circuit as in claim 21 wherein said filter means comprises: an inverter which receives said fourth output signal and provides the complement of said fourth output signal;   a NAND gate having a first input terminal, a second input terminal and an output terminal, said output terminal providing said fifth output signal;   a conductor which provides said complement of said fourth output signal to said first input terminal of said NAND gate;   a delay circuit having a time constant equal to said second selected period of time, wherein said delay circuit receives said complement of said fourth output signal and after said second selected period of time provides said complement of said fourth output signal to said second input terminal of said NAND gate;   whereby said NAND gate provides a logical zero output signal as said fifth output signal only if said fourth output signal remains a logical zero continuously for at least said second selected period of time.   
     
     
       35. A reset circuit as in claim 34 wherein said second means comprises a first CMOS inverter and said inverter of said filter means comprises a second CMOS inverter, each of said CMOS inverters having an input lead and an output lead wherein: said input lead of said first CMOS inverter receives said third output signal;   said output lead of said first CMOS inverter is tied to said input lead of said second CMOS inverter; and   said complement of said fourth output signal is provided on said output lead of said second CMOS inverter.   
     
     
       36. A reset circuit as in claim 35 wherein; each of said CMOS inverters comprises an unimplanted P channel enhancement mode transistor and an N channel enhancement mode transistor; and   said third selected value is the threshold voltage of said unimplanted P channel enhancement mode transistor.   
     
     
       37. A reset circuit as in claim 21 wherein said filter means comprises: a conductor having a first end connected to said input terminal of said filter means;   a logic gate having a first input terminal, a second input terminal and an output terminal wherein a second end of said conductor is connected to said first input terminal of said logic gate and said output terminal of said logic gate is said output terminal of said filter means;   a delay circuit having an input lead, an output lead and a time constant, wherein said input lead of said delay circuit is connected to said input terminal of said filter means and said output lead of said delay circuit is connected to said second input terminal of said logic gate; and further wherein   said time constant of said delay circuit is said second selected time period.   
     
     
       38. A reset circuit as in claim 37 wherein said delay circuit comprises: a first CMOS inverter having an input terminal and an output terminal, said input terminal of said first CMOS inverter being connected to said input lead of said delay circuit;   a resistive means having a first lead and a second lead, said first lead being connected to said output terminal of said first CMOS inverter;   a first capacitive means having a first plate and second plate, said first plate being connected to said second lead of said resistive means and said second plate being connected to a reference voltage;   a second CMOS inverter having an input terminal, and an output terminal, said input terminal being connected to said first plate of said first capacitive means; and   a second capacitive means having a first plate and a second plate, said first plate being connected to said power supply voltage and said second plate being connected to said output terminal of said second CMOS inverter and to said output lead of said delay circuit.   
     
     
       39. A reset circuit as in claim 38 wherein said first CMOS inverter comprises a P channel enhancement mode transistor and an N channel enhancement mode transistor;   said second CMOS inverter comprises an unimplanted P channel enhancement mode transistor and an N channel enhancement mode transistor; and   said resistive means comprises an N channel enhancement mode transistor having a first drain/source connected to said first lead of said resistive means, a second drain/source connected to said second lead of said resistive means and a gate connected to said power supply voltage.   
     
     
       40. A reset circuit as in claim 38 wherein said first CMOS inverter and said second CMOS inverter each comprise a P channel enhancement mode transistor and an N channel enhancement mode transistor; and   said resistive means comprises a transmission gate having an input terminal and an output terminal wherein said input terminal of said transmission gate is connected to said first lead of said resistive means and said output terminal of said transmission gate is connected to said second lead of said resistive means.   
     
     
       41. A reset circuit which comprises: means for sensing when a power supply voltage is applied to a circuit and for providing a first output signal of a first selected time in response thereto; and   means for sensing when said power supply voltage drops beneath a selected value for a time period in excess of a second selected time and for generating a second output signal in response thereto;   means for receiving said first and second output signals, and in response to receiving either of said first and second output signals, providing a reset signal during the time period when either of said first and second output signals is being received.   
     
     
       42. A reset circuit as in claim 41 in which said means for sensing when a power supply voltage is applied to a circuit and for providing a first output signal of said first selected time comprises a power-on reset circuit which provides said first output signal for said first selected time in response to said power supply voltage rising above a first selected level and after said first selected time has passed providing a signal complementary to said first output signal. 
     
     
       43. A reset circuit as in claim 42 in which said power-on reset circuit comprises: a delay circuit, responsive to said supply voltage for providing a first intermediate signal, said delay circuit comprising: a resistive means having an output terminal and an input terminal to which said power supply voltage is applied, wherein said resistive means conducts if and only if said power supply voltage rises above a second selected level, and wherein said first intermediate signal is provided to said output terminal of said resistive means after said supply voltage rises above said second selected level; and   a capacitor having a first and a second plate, said first plate of said capacitor being connected to said output terminal of said resistive means, said second plate of said capacitor being connected to a reference voltage; and     an initializing circuit providing said first output signal in response to said supply voltage rising above said first selected level after receiving said first intermediate signal;   wherein said first intermediate signal rises above a third selected value on said output terminal of said resistive means said first selected time after said supply voltage rises above said first selected value such that after said first selected time said initializing circuit provides said signal complementary to said first output signal.   
     
     
       44. A reset circuit as in claim 41 in which said means for sensing when said power supply voltage drops beneath a selected value for a time period in excess of said second selected time and for generating a second output signal comprises: first means, having a power supply terminal and a first means output terminal, for providing a first means output signal in response to said power supply voltage rising above a second selected value;   second means for receiving said first means output signal and for providing a second means output signal in response to the power supply voltage rising above a third selected value, wherein said second means output signal has a level greater than the level of said first means output signal if said power supply voltage is greater than a fourth selected value and said second means output signal has a level less than said level of said first means output signal if said power supply voltage is less than said fourth selected value; and   filter means for receiving said second means output signal and generating said second output signal having a first value if said second means output signal has a first selected value or if said second means output signal has a second selected value for less than said second selected time, and having a second value if said second means output signal has a second selected value for greater than said second selected time.   
     
     
       45. A reset circuit as in claim 44 wherein said filter means comprises: an inverter which receives said second means output signal and provides the complement of said second means output signal;   a NAND gate having a first input terminal, a second input terminal and an output terminal, said output terminal providing said second output signal;   a conductor which provides said complement of said second means output signal to said first input terminal of said NAND gate;   a delay circuit having an input terminal, an output terminal and a time constant equal to said second selected time, wherein said input lead of said delay circuit receives said complement of said second means output signal and after said second selected time provides said complement of said second means output signal to said second input terminal of said NAND gate;   whereby said NAND gate provides a logical zero output signal as said second output signal only if said second means output signal remains a logical zero continuously for at least said second selected time.   
     
     
       46. A reset circuit as in claim 45 wherein said delay circuit comprises at least two inverters, at least one capacitive means and at least one resistive means connected in series. 
     
     
       47. A reset circuit as in claim 46 wherein said delay circuit comprises a first inverter having its input terminal connected to receive said complement of said second means output signal, resistive means comprising an N channel transistor having a first drain/source connected to the output terminal of said first inverter and a control terminal connected to receive said power supply voltage, capacitive means comprising a transistor having both drain/source terminals connected to a reference voltage and a control terminal connected to a second drain/source of said N channel transistor, a second inverter having its input terminal connected to said second drain/source of said N channel transistor, and capacitive means comprising a transistor having both drain/source terminals connected to receive said power supply voltage and a control terminal connected to an output terminal of said second inverter, said output terminal of said second inverter also being connected to said output terminal of said delay circuit. 
     
     
       48. A reset circuit as in claim 44 wherein said filter means comprises: a logic gate having a first input terminal, a second input terminal and an output terminal, said output terminal providing said second output signal;   a conductor which provides said second means output signal to said first input terminal of said logic gate;   a delay circuit having an input terminal, an output terminal and a time constant equal to said second selected time, wherein said input lead of said delay circuit receives said second means output signal and after said second selected time provides said second means output signal to said second input terminal of said logic gate;   whereby said logic gate provides said reset signal as said second output signal only if said second means output signal remains a logical zero continuously for at least said second selected time.   
     
     
       49. A reset circuit as in claim 41 in which said means for receiving said first and second output signals and providing a reset signal comprises a NAND gate.