Voltage superposing circuit for an electronic tuner

Abstract

A pulse signal whose duty ratio differs for selected channels is coupled with the base of a first transistor as a switching transistor. The switching transistor is connected at the collector to a voltage source via a load resistor, and at the emitter to a reference potential point. An inverted pulse signal, which is derived from the collector of the first transistor, is rectified by a rectifying filter including a capacitor, and subsequently is applied to a tuning voltage terminal of an electronic tuner. A DC voltage proportional to an AFT voltage is applied to the base of a second transistor whose collector-emitter major current path is connected between a charge/discharge path of the capacitor and the reference potential point. A current flow through the major current path for a period of time, which differs for selected channels.

What is claimed is: 
     
       1. A voltage superposing circuit for supplying a tuning signal including the superposition of a channel select voltage on an automatic fine tuning (AFT) voltage to a tuning voltage terminal of an electronic tuner, said voltage superposing circuit comprising: a first transistor, with a switching function, for inverting the channel select pulse signal, the base of said first transistor being supplied with a channel select pulse signal, the collector thereof being connected through a load resistor to a voltage source, and the emitter thereof being connected to a reference potential point, said channel select pulse signals of the respective channels having different duty ratios and hence the ratios of the on- and off-periods of said first transistor differing for the respective channels;   voltage supply means for rectifying and smoothing a pulse signal at the collector of said first transistor and supplying the rectified and smoothed pulse signal to the tuning voltage terminal of the electronic tuner, said voltage supply means containing capacitive means, being coupled with said voltage source in a DC mode, for charging and discharging under control of the switching operation of said first transistor; and   transistor means of which the base is supplied with a DC voltage proportional to said AFT voltage, and the collector-emitter major current path is connected between a charge/discharge path of said capacitive means and the reference potential point.   
     
     
       2. The circuit according to claim 1, wherein said capacitive means includes a first capacitor, and   said voltage supply means includes:   a second transistor of which the collector is connected to said voltage source, and the emitter is connected through a second resistor to the reference potential point;   rectifying means for rectifying the pulse signal at the collector of said first transistor, said rectifying means containing a series circuit made up of said first capacitor and a third resistor connected between the collector of said first transistor and the reference potential point; and   smoothing means for smoothing the rectified pulse signal from said rectifying means, said smoothing means containing a series circuit made up of a second capacitor and a fourth resistor connected between the emitter of said second transistor and the reference potential point a node between said fourth resistor and said second capacitor being connected to the tuning voltage terminal of the electronic tuner.   
     
     
       3. The circuit according to claim 2, wherein said transistor means includes a third transistor, and   the collector of said third transistor is connected to a node between the collector of said first transistor and said third resistor, and the emitter of said third transistor is connected to the reference potential point by way of fifth and sixth resistors.   
     
     
       4. The circuit according to claim 3, further comprising switching means for switching a current flowing through a major current path of said third transistor in accordance with a selected frequency band. 
     
     
       5. The circuit according to claim 4, wherein said switching means includes a shortcircuiting means for shortcircuiting said sixth resistor when a specific frequency band is selected. 
     
     
       6. The circuit according to claim 5, wherein said shortcircuiting means includes: a terminal for receiving a voltage signal corresponding to a selected frequency band;   a series circuit made up of seventh and eighth resistors connected between said terminal and the reference potential point; and   a fourth transistor of which the base is connected to a node between said seventh and eighth resistors, the collector is connected to a node between said fifth and sixth resistors, and the emitter is connected to the reference potential point.   
     
     
       7. The circuit according to claim 2, wherein said transistor means includes a third transistor, and   the collector of said third transistor is connected to a node between said fourth resistor and said second capacitor, and the emitter of said third transistor is connected to the reference potential point by way of fifth and sixth resistors.   
     
     
       8. The circuit according to claim 7, further comprising switching means for switching a current flowing through a major current path of said third transistor in accordance with a selected frequency band. 
     
     
       9. The circuit according to claim 8, wherein said switching means includes a shortcircuiting means for shortcircuiting said sixth resistor when a specific frequency band is selected. 
     
     
       10. The circuit according to claim 9, wherein said shortcircuiting means includes: a terminal for receiving a voltage signal corresponding to a selected frequency band;   a series circuit made up of seventh and eighth resistors connected between said terminal and the reference potential point; and   a fourth transistor of which the base is connected to a node between said seventh and eighth resistors, the collector is connected to a node between said fifth and sixth resistors, and the emitter is connected to the reference potential point.   
     
     
       11. The circuit according to claim 1, wherein said capacitive means includes a plurality of first capacitors, and   said voltage supply means includes:   a second transistor of which the collector is connected to said voltage source and the emitter is connected through a second resistor to the reference potential point;   rectifying means for rectifying the pulse signal at the collector of said first transistor, said rectifying means making up of a first series circuit and said plurality of first capacitors, said first series circuit making up of a plurality of third resistors connected between the collector of said first transistor and the base of said second transistor, and said plurality of first capacitors being respectively connected between said third resistors and the reference potential point and between the base of said second transistor and the reference potential point; and   smoothing means for smoothing the rectified pulse signal from said rectifying means, said smoothing means containing a second series circuit made up of a fourth resistor and a second capacitor, said second series circuit being connected between the emitter of said second transistor and the reference potential point, and a node between said forth resistor and said second capacitor being connected to the tuning voltage terminal of the electronic tuner.   
     
     
       12. The circuit according to claim 11, wherein said transistor means includes a plurality of third transistors, and   the collector of each third transistor is connected to any of the collector of said first transistor, nodes between said third resistors and said first capacitors, the base of said second transistor, and the node between said forth resistor and said second capacitor.   
     
     
       13. The circuit according to claim 12, wherein said third transistors are provided corresponding to receiving frequency bands, respectively. 
     
     
       14. The circuit according to claim 13, further comprising bias means, provided respectively corresponding to said third transistors, for providing bias voltages respectively appropriate to the receiving frequency bands to the emitter of said third transistor. 
     
     
       15. The circuit according to claim 14, wherein each of said bias means includes: terminals for respectively receiving voltages corresponding to the receiving frequency bands; and   fourth transistors of which the bases are respectively connected through fifth resistors to said terminals, the collectors are respectively connected to sixth resistors to said third transistors; and the emitters are connected to the reference potential point.