CMOS RAM with merged bipolar transistor

Abstract

A CMOS, N-well, P-channel static RAM cell with merged bipolar transistors as its output drivers.

What is claimed is: 
     
       1. An integrated circuit memory cell comprising, a substrate of a first conductivity type semiconductor material;   a region of a second conductivity type semiconductor material located in said substrate and forming a well therein having a surface;   six regions of said first conductivity type semiconductor material located in said well and forming six pockets therein arranged in two sets of three pockets each, the first and third pocket of each set being separated from the second along the surface of said well by sections of said well material comprising four in number;   a thin oxide layer located on said four sections of said well material forming insulator layers;   gate electrodes located on said four insulator layers;   said gate electrodes and said six pockets comprising four field effect transistors, namely two data storage transistors and two drive transistors;   one pocket in each set having a region of said second conductivity type semiconductor material located in it, each said region in a pocket comprising the emitter of a bipolar transistor with the pocket it is located in comprising the base and said well comprising the collector of said associated bipolar transistor.   
     
     
       2. An integrated circuit memory cell as in claim 1, wherein said first conductivity type semiconductor material is P-type material. 
     
     
       3. An integrated circuit memory cell as in claim 2, wherein said second type semiconductor material is N-type material. 
     
     
       4. An integrated circuit memory cell as in claim 3, wherein each said field effect transistor comprises source and drain regions and a gate electrode. 
     
     
       5. An integrated circuit memory cell as in claim 4, wherein the source regions of said data storage transistors are connected together and the drain region of each is connected to the gate electrode of the other. 
     
     
       6. An integrated circuit memory cell as in claim 5, wherein the source region of one of said drive transistors is connected to the gate electrode of one data storage transistor and the source region of the other drive transistor is connected to the gate electrode of the other data storage transistor. 
     
     
       7. An integrated circuit memory cell as in claim 6, wherein the drain region of one of said drive transistors is connected to the base of one of said bipolar transistors and the drain region of the other drive transistor is connected to the base of the other bipolar transistor. 
     
     
       8. An integrated circuit memory cell as in claim 7, wherein the collectors of said bipolar transistors are connected together and the emitters are the outputs of said memory cell. 
     
     
       9. An integrated circuit memory cell as in claim 8, including two PNP-type transistors, one for connecting the emitter of one of said bipolar transistors to a discharging voltage level and the other for connecting the emitter of the other bipolar transistor to said discharging potential.