Reconfigurable pipelined processor

Abstract

The reconfigurable pipelined processor includes a plurality of memory devices and arithmetic units interconnected by cross bars for transferring raw and processed data therebetween. A counter is connected with the cross bar to provide a source of addresses for the memory devices. At least one variable tick delay device is connected with each memory and arithmetic unit to variably control the input and output operations thereof to selectively delay the memory devices and arithmetic units to align the data for processing in a selected sequence.

What is claimed is: 
     
       1. A reconfigurable pipelined processor for processing data, comprising: (a) a plurality of memory devices for storing bits of data;   (b) a plurality of arithmetic units for performing arithmetic functions with the data;   (c) cross bar means for connecting said memory devices with said arithmetic units for transferring data therebetween;   (d) at least one counter connected with said cross bar means for providing a source of addresses to said memory devices;   (e) at least one variable tick delay device connected with each of said memory devices and arithmetic units; and   (f) means for providing control bits to said variable tick delay device for variably controlling the input and output operations thereof to selectively delay said memory devices and arithmetic units to align the data for processing in a selected sequence.   
     
     
       2. Apparatus as defined in claim 1, wherein a variable tick delay device is connected with each input and output of each of said memory devices and arithmetic units. 
     
     
       3. Apparatus as defined in claim 2, and further comprising at least one independent variable tick delay device connected with said cross bar means for re-aligning data during processing in a selected sequence. 
     
     
       4. Apparatus as defined in claim 3, wherein said variable tick delay devices each comprise a plurality of multiplexers each having a plurality of pipelined registers connected therewith, the number of registers in the pipelined data path being determined by the control bits delivered to each multiplexer. 
     
     
       5. A method for processing data in a pipelined processor including a plurality of memory devices and arithmetic units interconnected by cross bars, comprising the steps of (a) loading input data into the memory devices;   (b) selectively operating the cross bars to selectively transfer the data between the memory devices and the arithmetic units in accordance with a predetermined clocking rate;   (c) controlling the operation of the arithmetic units to perform arithmetic functions with the data;   (d) varying the delay of the input and output of data from the memory devices and arithmetic units relative to the clocking rate to align the data for processing in a selected sequence; and   (e) unloading the processed data from the memory device.   
     
     
       6. The method as defined in claim 5, and further comprising the step of controlling read/write signals to the memory devices to facilitate the transfer of data relative thereto.