CMOS voltage divider circuits

Abstract

A CMOS fractional reference source or voltage divider circuit includes a string (chain) of CMOS pairs of transistors connected with their source-drain circuits in series and with ends of the string being connected across an input power (voltage) supply. The P-channel transistors are all matched to one another in a one to one ratio, the N-channel transistors are all similarly matched to one another. Output terminals are connected at the nodes between pairs of transistors. Accurate tracking of the voltage of the power supply is achieved by connecting each gate of the chain in a manner to insure the same source-to-gate voltage on each transistor of the pair. In the preferred form, the string comprises two pairs of CMOS transistors and the voltage appearing at the output terminal thereof is equal to one half of the voltage of the power supply.

What is claimed is: 
     
       1. A voltage divider circuit for connection across a power supply comprising: a plurality of pairs of complementery field effect transistors each transistor having a source and a drain defining the ends of a conduction path and a control electrode, the transistors being connected in a string so that their separate source-drain paths form a series circuit for connection across the power supply, each of the pairs of transistors comprising an N-channel field effect transistor and a P-channel field effect transistor;   an output node between each successive pairs of transistors where an output voltage may be abstracted; and   for each and every pair of complementary transistors, means for connecting the gate of the first transistor of a pair and the source of the second transistor of that pair to one point of potential on the string and means for connecting the gate of the second transistor of the pair and the source of the first transistor to another point of potential on the string whereby the source-to-gate voltages of the two transistors of each pair of complementary transistors in the string are equal.   
     
     
       2. The voltage divider circuit of claim 1 in which there are four transistors in the string of which the two P-channel transistors are matched to one another in essentially a one to one ratio and the two N-channel transistors are matched to one another in essentially a one to one ratio and there is available one half the supply voltage at an output terminal coupled to the output node between the two pairs of complementary transistors. 
     
     
       3. The voltage divider circuit of claim 2 in which the first transistor of the string has its gate connected to the output terminal, the second transistor has its gate connected to one of two ends of the string, the third transistor has its gate connected to the other end of the string, and the fourth transistor has its gate connected to the output terminal. 
     
     
       4. The voltage divider circuit of claim 3 wherein the transistors are metal-oxide-silicon (MOS) type transistors. 
     
     
       5. The voltage divider circuit of claim 3 wherein the transistors are junction field effect transistors. 
     
     
       6. The voltage divider circuit of claim 3 wherein the transistors are silicon-on-sapphire field effect transistors. 
     
     
       7. The voltage divider circuit of claim 1 in which the number of pairs of complementary transistors is two or greater. 
     
     
       8. The voltage divider circuit of claim 7 wherein the transistors are metal-oxide-silicon (MOS) transistors. 
     
     
       9. The voltage divider circuit of claim 7 wherein the transistors are junction field effect transistors. 
     
     
       10. The voltage divider circuit of claim 7 wherein the transistors are silicon-on-sapphire field effect transistors. 
     
     
       11. In combination: first and second power terminals for the application therebetween of a source of operating potential;   a first P-channel type field effect transistor, a second N-channel type field effect transistor, a third P-channel type field effect transistor and a fourth N-channel type field effect transistor;   each of the transistors having a gate electrode and drain and source electrodes defining the ends of a conduction path and the source-drain paths of the first, second, third and fourth transistors being connected successively in series between said first and second power terminals;   means connecting the gate of the first transistor to the sources of the second and third transistors;   means connecting the gate of the second transistor to the source of the first transistor;   means connecting the gate of the third transistor to the source of the fourth transistor;   means connecting the gate of the fourth transistor to the sources of the second and third transistors; and   an output terminal being coupled to the sources of the second and third transistors.   
     
     
       12. The combination of claim 11 wherein the first and third transistors are matched in essentially a one to one ratio, and the second and fourth transistors are matched in essentially a one to one ratio. 
     
     
       13. The combination of claim 12 wherein the field effect transistors are metal-oxide-silicon (MOS) type transistors. 
     
     
       14. The combination of claim 12 wherein the transistors are junction field effect transistors. 
     
     
       15. The voltage divider circuit of claim 12 wherein the transistors are silicon-on-sapphire field effect transistors. 
     
     
       16. In combination: a first field effect transistor of the first conductivity type, a second field effect transistor of the opposite conductivity type, a third field effect transistor of the first conductivity type, and a fourth field effect transistor of the opposite conductivity type;   each of the transistors having a gate and first and second output terminals;   the second output terminal of the first transistor being coupled to the first output terminal of the second transistor;   the second output terminal of the third transistor being coupled to the first output terminal of the fourth transistor;   the gate of the first transistor being coupled to the second output terminal of the second transistor and to the first output terminal of the third transistor;   the gate of the second transistor being coupled to the first output terminal of the first transistor;   the gate of the third transistor being coupled to the second output terminal of the fourth transistor;   the gate of the fourth transistor being coupled to the second output terminal of the second transistor and to the first output terminal of the third transistor;   a power supply being coupled between the first output terminal of the first transistor and the second output terminal of the fourth transistor;   an output terminal being coupled to the second output terminal of the second transistor and to the first output terminal of the third transistor; and   the first and third transistors being matched in essentially a one to one ratio, and the second and fourth transistors being matched in essentially a one to one ratio.   
     
     
       17. The combination of claim 16 further comprising: the first and second transistors comprise a first pair of complementary transistors and the third and fourth transistors comprise a second pair of complementary transistors; and   one or more additional pairs of complementary transistors serially coupled to the first and second pairs of complementary transistors.   
     
     
       18. Circuitry comprising: a plurality of pairs of complementary field effect transistors connected in a string so that their separate source-drain circuits form a series circuit which is coupled by one end thereof to a first terminal and is coupled by a second end thereof to a second terminal;   the gate of each first transistor of a pair of transistors being coupled to the source of the second transistor of that pair of transistors; and   the gate of each second transistor of a pair of transistors being coupled to the source of the first transistor of that pair of transistors.   
     
     
       19. A voltage divider circuit comprising: first and second power terminals for the application therebetween of a potential to be divided;   M-pairs of complementary field effect transistors, each transistor having source and drain electrodes defining the ends of a conduction path and a control electrode, each pair of transistors comprising a N and a P channel field effect transistor;   means connecting the drain of the first transistor of each pair of transistors to the drain of the second transistor of that pair of transistors, whereby the conduction paths of the two transistors of each pair are connected in series, and means connecting the control electrode of the first transistor of each pair of transistors to the source electrode of the second transistor of that pair and the control electrode of the second transistor of each pair of transistor to the source electrode of the first transistor of that pair, whereby the control electrode-to-source voltage of the first transistor of each pair equals the control electrode-to-source voltage of the second transistor of that pair; and   means connecting the M pairs of complementary transistors in series between said first and second power terminals; where M is an integer greater than one (1).