High power buffer circuit with low noise

Abstract

A CMOS output buffer circuit is reduced its output pulse noise and excess current which runs through the CMOS when it is switched ON and OFF. In the gate circuits of p and n channel FETs of the CMOS output buffer circuit, a time constant circuit is inserted. The time constant circuit slightly slows down the voltage variation of input signals to the gates, so the rush current which runs through the output FETs for charging up or discharging the load capacitance is decreased. So, the dI/dt noise is reduced, but the total switching time of the output circuit is not so much affected. By the difference of time lags between the build up and trailing edges of input pulses for both output FETs, one of the output FETs becomes conductive always after the other one is cut off. So, the excess current is reduced. The time constant circuit is composed of a series connected resistor and inverter circuit, connected between positive and negative voltage sources. The time constant circuit many be provided in both or one of the driving circuits for the output FETs. The resistors may be replaced by FETs having proper internal resistances.

What is claimed are as follows: 
     
       1. A complementary metal oxide semiconductor (CMOS) type output buffer circuit for suppressing impulsive output noise caused by a rapid variation of a large rush current in an output stage, comprising: an input terminal for receiving an input signal;   a first voltage source for providing a first voltage;   a second voltage course for providing a second voltage;   a p channel output field effect transistor (FET) having a gate;   an n channel output FET having a gate, said p channel output FET and said n channel output FET being connected to each other in series between said first and second voltage sources, said output FETs being commonly connected together at the respective drains thereof and providing an output signal at an output terminal at said common connection;   a first time constant circuit, connected between said input terminal and one of the gates of said p and n channel output FETs, for slowing down the time rate of change of a signal voltage applied to one of the gates of said p and n channel output FETs in response to the input signal; and   a second time constant circuit, connected between said input terminal and the other one of the gates of said p and n channel output FETs, for slowing down the time rate of change of a signal voltage applied to said other one of the gates of said p and n channel output FETs in response to the input signal.   
     
     
       2. The CMOS output buffer circuit as set forth in claim 1, wherein said first time constant circuit is connected between said input terminal and the gate of said p channel output FET. 
     
     
       3. The CMOS output buffer circuit as set forth in claim 1, wherein said first time constant circuit is connected between said input terminal and the gate of said n channel output FET. 
     
     
       4. The CMOS output buffer circuit as set forth in claim 1, wherein: said first time constant circuit comprises a driver circuit for driving said p channel output FET and a resistor connected in series between said driver circuit and one of the first and second voltage sources.   
     
     
       5. The CMOS output buffer circuit as set forth in claim 2, wherein: said first time constant circuit comprises a driver circuit for driving said p channel output FET and a resistor connected in series between said driver circuit and the second voltage source.   
     
     
       6. The CMOS output buffer circuit as set forth in claim wherein: said first time constant circuit comprises a driver circuit for driving said n channel output FET and a resistor connected in series between said driver circuit and the first voltage source.   
     
     
       7. The CMOS output buffer circuit as set forth in claim 1, wherein: said first time constant circuit is connected to the gate of said p channel output FET and comprises a driver circuit for driving said p channel output FET and a resistor connected in series between said driver circuit and the second voltage source; and   said second time constant circuit is connected to the gate of said n channel output FET and comprises a driver circuit for driving said n channel output FET and a resistor connected in series between said driver circuit and the first voltage source.   
     
     
       8. The CMOS output buffer circuit as set forth in claim 1, wherein: said first time constant circuit is connected to the gate of said p channel output FET and comprises a driver circuit for driving said p channel output FET and an n channel FET connected in series between said driver circuit and the second voltage source, and the gate of said n channel FET is connected to the first voltage source; and   said time constant circuit is connected to the gate of said n channel output FET and comprises a driver circuit for driving said n channel output FET and a p channel FET connected in series between said driver circuit and the first voltage source, and the gate of said p channel FET is connected to the second voltage source.   
     
     
       9. The CMOS output buffer circuit as set forth in claim 4, 5, 6, 7 or 8 wherein: said driver circuit is an inverter composed of a p channel FET and an n channel FET connected in series to each other.   
     
     
       10. The CMOS output buffer circuit as set forth in claim 9, wherein: said p and n channel output FET have a lower internal resistance than those of the p and an n channel FETs in the inverter.   
     
     
       11. A complementary metal oxide semiconductor (CMOS) type output buffer circuit comprising: an input terminal (1) for receiving control signals;   an output terminal (10) for providing output signals;   a first voltage source for providing a first voltage;   a second voltage source for providing a second voltage;   a p channel output field effect transistor (FET) (71) having a low internal resistance, source of said p channel output FET being connected to said first voltage source;   an n channel output FET (72) having a low internal resistance, drain of said n channel output FET (72) being connected to drain of said p channel output FET (71) and to said output terminal (10), and source of said n channel output FET (72) being connected to the second voltage source;   time constant circuits (61, 62) respectively connected to gates of said p channel output FET (71) and n channel output FET (72), wherein, said time constant circuit (61) which is connected to the gate of said p channel output FET comprises an inverter circuit (51) composed of a series connected p channel FET (511) and n channel FET (512), for driving the gate of said p channel output FET (71), and a resistor (R1) connected between source of said n channel FET (512) and the second voltage source; and   said time constant circuit (62) which is connected to the gate of said n channel output FET (72) comprises an inverter circuit (52) composed of a series connected p channel FET (521) and n channel FET (522), for driving said n channel output FET (72), and a resistor (R2) connected between source of said p channel FET (521) and the first voltage source, and   gates of said p channel FETs (511, 521) and n channel FETs (512, 522) of said inverters are connected in common to said input terminal (1).   
     
     
       12. The CMOS output buffer circuit as set forth in claim 11, wherein: said resistors (R1, R2) being respectively composed of internal resistance of n channel FET (Q1) and p channel FET (Q2) of which gates are respectively connected to one of said first or second voltage sources.   
     
     
       13. A complementary metal oxide semiconductor (CMOS) type output buffer circuit comprising: an input terminal (1) for receiving control signals;   an output terminal (10) for providing output signals;   a first voltage source for providing a first voltage;   a second voltage source for providing a second voltage;   a p channel output field effect transistor (FET) (71) having a low internal resistance, gate and source of which being connected respectively to said input terminal (1) and to said first voltage source;   an n channel output FET (72) having a low internal resistance, drain of which being connected to drain of said p channel output FET (71) and to said output terminal (10), and source of said n channel output FET (72) being connected to the second voltage source;   a time constant circuit (62) connected to the gate of said n channel output FET (72), said time constant circuit (62) comprises an inverter circuit (52) composed of a series connected p channel FET (521) and n channel FET (522), for driving the gate of said n channel output FET (72), and a resistor (R2) connected between the source of said p channel FET (521) and the first voltage source; and   a second inverter (2') of which input terminal being connected to said input terminal (1), and output terminal being connected in common to the gates of said p channel FET (521) and n channel FET (522) of said inverter circuit (52).   
     
     
       14. The CMOS output buffer circuit as set forth in claim 13, wherein said resistor comprises the internal resistance of a p channel FET connected to said first voltage source. 
     
     
       15. Complementary metal oxide semiconductor (CMOS) type output buffer circuit comprising: an input terminal (1) for receiving control signals;   an output terminal (10) for providing output signals;   a first voltage source for providing a first voltage;   a second voltage source for providing a second voltage;   a p channel output field effect transistor (FET) (71) having a low internal resistance, source of which being connected to said first voltage source;   an n channel output FET (72) having a low internal resistance, drain of which being connected to drain of said p channel output FET (71) and to said output terminal (10), and source of said n channel output FET (72) being connected to the second voltage source;   a time constant circuit (61) connected to the gate of said n channel output FET (71), said time constant circuit (61) comprises an inverter circuit (51) composed of a series connected p channel FET (511) and n channel FET (512), for driving the gate of said p channel output FET (71), and a resistor (R1) connected between the source of said n channel FET (512) of the inverter circuit (51) and the second voltage source; and   a second inverter (2') of which input terminal being connected to said input terminal (1), and output terminal being connected in common to the gates of said p channel FET (511) and n channel FET (512) of said inverter circuit (51).   
     
     
       16. The CMOS output buffer circuit as set forth in claim 15, wherein said resistor comprises the internal resistance of an n channel FET connected to said second voltage source.