Synchronization method and elastic buffer circuit

Abstract

An asynchronous communication system includes a clock recovery circuit (2) to which the received signal (1) is applied and which provides recovered data (3) to a frame delimiter detector (4). The frame delimiter detector in turn generates a frame start signal to a frame sync generator (16) and provides asynchronous data (5) to an elastic buffer (7) which provides as its output the synchronized data (8). The clock recovery circuit also provides a recovered clock signal (9) to a clock guarding circuit (12). The clock guarding circuit (12) receives a local clock signal (11) and produces a guarded clock signal (13) and a data clock signal (14), both of which are supplied to the frame sync generator and the elastic buffer. The frame sync generator produces a frame sync signal having a duration determined by the active edges of the guarded clock and data clock signals, and this signal is used to load a mask pattern in the elastic buffer. The synchronization method uses the guarded clock signal derived from the recovered clock signal so that the recovered clock signal cannot switch within certain zones on either side of each active edge of the data clock signal.

Having thus described my invention, what I claim as new and desire to secure by Letters Patent is as follows: 
     
       1. A synchronization circuit for asynchronous data communication comprising: clock recovery circuit means for receiving a data signal and generating a recovered data signal and a recovered clock signal;   frame delimiter detector means connected to receive said recovered data signal for generating an asynchronous data signal and a frame start pulse;   clock guarding circuit means responsive to a local clock signal and said recovered clock signal for generating a guarded clock signal and a data clock signal, said local clock signal and said recovered clock signal having a nominal frequency equal to a data bit rate of said recovered data signal, and said guarded clock signal being derived from the recovered clock signal so that the recovered clock signal cannot switch within a certain zone associated with each active edge of the local clock signal;   frame sync generator means responsive to said frame start pulse for generating a frame sync signal having a duration determined by active edges of said guarded clock and data clock signals; and   elastic buffer means controlled by said guarded clock signal and said data clock signal and responsive to said asynchronous data signal and said frame sync signal for generating a synchronized output data signal.   
     
     
       2. The synchronization circuit recited in claim 1 wherein said elastic buffer means comprises: shift register means connected to receive said asynchronous data signal and shifted by said guarded clock signal;   multiplexer means connected to parallel outputs of said shift register means for selecting one of said outputs as a data output;   mask register means initially loaded with a mask bit pattern in response to said frame sync signal and clocked by said data clock signal for providing a control output to said multiplexer means;   multiplexer control means responsive to said data clock and guarded clock signals and said mask bit pattern for controlling said multiplexer means; and   output means for outputing said data output in response to said data clock signal.   
     
     
       3. The synchronization circuit recited in claim 2 wherein said multiplexer control means comprises: shifter means receiving said mask bit pattern from said mask register means and providing said control output shifted left or right or not shifted depending on control inputs to said shifter means; and   control means responsive to said guarded clock and data clock signals for generating said control inputs whereby independently set guard zones are set before and after active edges of said data clock signal.   
     
     
       4. The synchronization circuit recited in claim 3 wherein said clock guarding circuit means comprises: latch means clocked by said recovered clock signal;   first delay element means for producing a delayed local clock signal;   hold means responsive to said local clock signal and said delayed local clock signal for inhibiting said latch means;   second delay element means for producing a delayed recovered clock signal;   gating means enabled by said latch means for gating said delayed recovered clock signal to produce said guarded clock signal; and   third delay element means connected to said first delay element means for producing said data clock signal whereby said first and third delay element means establish said guard zones.   
     
     
       5. The synchronization circuit recited in claim 2 wherein said multiplexer means comprises a plurality of tri-state devices having inputs connected to respective stages of said shift register means and outputs connected in common, and said output means is a flip-flop having an input connected to the commonly connected outputs of said tri-state devices and clocked by said data clock signal.