Defect detector circuit for inductive load driving circuit

Abstract

A defect detector circuit for an inductive load driving circuit which has a surge comparator circuit for comparing a surge generated from an inductive load when the current of the inductive load is interrupted with a reference value on the basis of an output from a surge absorber circuit for absorbing the surge, and a surge time deciding circuit for outputting a defect signal when a time that the surge amount exceeds the reference value does not fall within a set range on the basis of the output from the surge comparator circuit.

What is claimed is: 
     
       1. A defect detector circuit comprising: a surge comparator circuit connected to receive a surge voltage generated from an inductive load and which produces a reference voltage, compares the surge voltage with the reference voltage, and produces a comparator output signal which is in a first logic state during a first time period wherein the surge voltage exceeds the reference voltage, and in a second logic state otherwise;   a surge time deciding circuit connected to receive the comparator output signal and including:   (a) a first one-shot multivibrator connected to receive the comparator output signal and to produce a first output pulse for a second time period when the comparator output signal changes from the second logic state to the first logic state, and   (b) a first flip-flop with a data terminal connected to receive the comparator output signal and a timing terminal connected to receive the first multivibrator output pulse and to store the signal at the data terminal when the first multivibrator output changes from the first logic state to the second logic state,   wherein the surge time deciding circuit outputs a signal in a first logic state normally and in a second logic state when a defect causes the first time period to be shorter than the second time period; and   a defect indicator circuit connected to indicate a defect in accordance with the output of the surge time deciding circuit.   
     
     
       2. A defect detector as claimed in claim 1 wherein said surge time deciding circuit further includes: (a) a second one-shot multivibrator connected to receive the comparator output signal and to produce a second output pulse for a fourth time period when the comparator output changes form the second logic state to the first logic state;   (b) a second flip-flop with a data terminal connected to receive the comparator output signal and a timing terminal connected to receive the second multivibrator output pulse and to store the signal at the data terminal when the second multivibrator output changes from the first logic state to the second logic state; and   (c) a logic circuit connected to receive the stored signals of the first and second flip-flips and to produce the output of the surge time deciding circuit;   wherein the fourth time period is longer than the second time period, and the surge time deciding circuit outputs a signal in the second logic state when a defect causes the first time period to be longer than the fourth time period.   
     
     
       3. A defect detector as claimed in claim 1 wherein said defect indicator circuit includes a lamp which lights when the output of the surge time deciding circuit is in the second logic state. 
     
     
       4. A defect detector as claimed in claim 1 wherein said surge comparator circuit comprises a voltage divider for providing a reference voltage and a comparator. 
     
     
       5. A defect detector as claimed in claim 1 wherein said surge comparator circuit comprises a zener diode connected to receive the surge voltage. 
     
     
       6. A defect detector as claimed in claim 1 wherein said surge time deciding circuit further includes: (a) a watchdog timer with an input terminal connected to the receive the comparator output signal and be reset by a transition of the comparator output signal from the second logic state to the first logic state, and an output terminal; and   (b) a logic circuit connected to receive the stored signal of the first flip-flop and the output of the watchdog timer and to produce the output of the surge time deciding circuit;   wherein the watchdog timer produces an output signal when the comparator output signal remains in the second logic state for a predetermined third time period longer than the second time period due to a defect which prevents the comparator output signal from changing from the second logic state to the first logic state.