Semiconductor memory device having controllable redundant scheme

Abstract

A semiconductor memory device having a controllable majority decision reading scheme is disclosed. The memory is featured in that a number of memory cells to be selected in one access cycle is varied by at least one control signal and a logic state of a read-out signal is determined by data derived from the desired number of memory cell on cells.

I claim: 
     
       1. A semiconductor memory device comprising a memory array of a plurality of memory cells arranged in rows and columns, a row selection circuit for selecting one of said rows of said memory array, means for receiving at least one control signal representing one of a first state and a second state, a column selection circuit responsive to column address signals and coupled to said receiving means to receive said at least one control signal for selecting a first number of column or columns of said memory array in a first mode and selecting a second number of columns of said memory array in a second mode, said second number being larger than said first number, a control circuit coupled to said receiving means and said column selecting circuit for setting said column selection circuit in said first mode when said at least one control signal assumes the first state and in said second mode when said at least one control signal assumes the second state, a data determination circuit coupled to said column selection circuit for generating an output signal having a logic state which is determined by data derived from said first number of column or columns when said at least one control signal assumes said first state and determined by data derived from said second number of columns when said at least one control signal assumes said second state, and output means coupled to said data determination circuit for outputting said output signal. 
     
     
       2. The memory device according to claim 1, in which columns of said memory array are classified into a plurality of groups of said second number, each of said groups having a third number of columns, and said column selection circuit includes a first column decoder having output terminals of said third number, a second column decoder having output terminals of said second number, and a logic circuit coupled to the output terminals of said first and second column decoders for selecting said first number of column or columns in one of said groups when said at least one control signal assumes said first state and selecting said said first number of column or columns in each of said groups thereby to select said second number of columns as a whole when said at least one control signal assumes said second state. 
     
     
       3. The memory device according to claim 1, in which said data determination circuit includes AND gates receiving said second number for majority decision of data derived from said second number of columns for producing a majority data among said received second number of data. 
     
     
       4. A semiconductor memory device comprising a memory array of memory cells, means for receiving at least one control signal representing a first state or a second state, an addressing circuit coupled to said receiving means to receive said at least one signal for selecting a first number of memory cell or cells when said control signal assumes a first state and selecting a second number of memory cells when said control signal assumes a second state, a data determination circuit coupled to said memory array and said receiving means for determinating a state from a data signal by data of said first number of memory cell or cells when said control signal assumes said first state and by data from said second number of memory cells when said control signal assumes said second state and output means for outputting said data signal. 
     
     
       5. A semiconductor memory device comprising a memory array of memory cells, means for receiving at least one control signal representing a first state or a second state, a first addressing circuit for selecting a first number of memory cell or cells, a second addressing circuit for selecting a second number of memory cells, a first control circuit coupled to said receiving means and said first and second addressing circuits for enabling said first addressing circuit when said at least one control signal is in said first state and enabling said second addressing circuit when said at least one control signal is in said second state different from said first state, a data determination circuit for determinating a state of a majority data signal by data from said first number of memory cell or cells selected by said first addressing circuit in a first mode and by data from said second number of memory cells selected by said second addressing circuit in a second mode, a second control circuit coupled to said receiving means and said data determination circuit for setting said data determination circuit in said first mode when said at least one control signal is in said first state and in said second mode when said at least one control signal is in said second state, and output means coupled to said data determination circuit for outputting said majority data signal. 
     
     
       6. The semiconductor memory device according to claim 5, in which each of said memory cells is a non-volatile type. 
     
     
       7. A semiconductor memory device comprising a plurality of word lines; a plurality of digit lines; a plurality of memory cells coupled to said word lines and said digit lines; means for receiving at least one control signal representing a first state or second state; a row selection circuit for selecting one of said word lines; a data line; a plurality of transfer gates, each of said transfer gates being coupled between said data line and each one of said digital lines, said transfer gates being classified into a plurality of transfer gate groups of a first number, each of said transfer gate groups including a plurality of transfer gates of a second number; a first column decoder having first decoded outputs of said first number, one of said first decoded outputs being selected; a second column decoder having second decoded outputs of said second number, one of said second decoded outputs being selected; a serial selection circuit having serial selection outputs of said first number, said serial selection outputs being sequentially selected one by one; a control selection circuit coupled to said receiving means and having control output terminals of said first number, said control selection circuit outputting said first decoded outputs to said control output terminals when said at least one control signal assumes said first state and outputting said serial selection outputs to said control output terminals when said at least one control signal assumes said second state different from said first state; and a plurality of drive decoder circuits of said first number provided for said transfer gate groups, each of said drive decoder circuits having a first input terminal coupled to one of said control output terminals, a plurality of second input terminals of said second number and a plurality of drive output terminals of said second number, said second input terminals being coupled to said second decoded outputs, said drive output terminals being coupled to the transfer gates of the associated transfer gate group, each of said drive decoder circuits selectively enabling one of the transfer gates of the first input terminal thereof is at a selective level. 
     
     
       8. The semiconductor memory device according to claim 7, in which each of said drive decoder circuits includes a plurality of NOR gates of said first number, each of said NOR gates including a first input node coupled to the first input terminal of the same drive decoder circuit, a second input node coupled to one of the second input terminals of the same drive decoder circuit, and an output node coupled to one of the drive output terminals of the same drive decoder circuit. 
     
     
       9. The semiconductor memory device according to claim 7, in which said control selection circuit including a plurality of first gates of said first number each receiving one of said first decoded outputs, a plurality of said gates of said first number each receiving one of said serial selection outputs, means for enabling said first gates when said at least one control signal assumes said first state, and means for enabling said second gates when said at least one control signal assumes said second state. 
     
     
       10. The semiconductor memory device according to claim 7, in which each of said memory cell is a non-volatile type memory cell.