Synchronizing circuit

Abstract

A pulse signal transfer control circuit is located between an input pulse detecting circuit for detecting the arrival of an externally applied input pulse and outputting a pulse signal with a predetermined pulse width, and an R-S flip-flop. The transfer control circuit prohibits the pulse signal from being transferred to the R-S flip-flop during a period in which the R-S flip-flop is set, a period of generation of a first internal clock signal, and a period of generation of a second internal clock signal, and allows the pulse signal to be transferred to the first R-S flip-flop during period in which the first and second clock signals are not generated and the period in which the first R-S flip-flop is reset.

What is claimed is: 
     
       1. A synchronizing circuit comprising: input pulse detecting means for detecting the arrival of an externally applied input pulse signal and generating a pulse signal of a predetermined width;   a first bistable circuit;   first latch means for latching the output signal from said first bistable circuit, in synchronism with a first internal clock signal;   second latch means for latching the output signal of said first bistable circuit, in synchronism with a second internal clock signal, which is different in phase from said first internal clock signal;   reset signal generating means which responds to the output signal from one of said first and second latch means which executed the latching operation, and supplies a reset signal to said first bistable circuit during a period of generation of the clock signal corresponding to the latch means which did not execute the latching operation;   output means for outputting the output signal from said reset signal generating means, in synchronism with one of said first and second clock signals; and   pulse signal transfer control means, which receives the pulse signal output from said detecting means, prohibits said pulse signal from being transferred to said first bistable circuit during a period in which said first bistable circuit is set, a period of generation of said first clock signal, and a period of generation of said second clock signal, and allows the pulse signal to be transferred to said first bistable circuit during a period in which said first and second clock signals are not generated and said period in which said first bistable circuit is reset.   
     
     
       2. A synchronizing circuit according to claim 1, in which said pulse signal transfer control means includes a second bistable circuit which is set by the pulse signal output from said detecting means, third latch means for latching the output signal of said second bistable circuit, in synchronism with said first or second clock signal, a fourth latch means for latching the output signal of said first bistable circuit, in synchronism with said first or second clock signal, and gate means, wherein said gate means prohibits the output signal of said third latch means from being transferred as a set signal to said first bistable circuit during a period in which said fourth latch means latches the output signal representing the set state of said first bistable circuit, a period of generation of said first clock signal, and allows the output signal from said third latch means to be transferred as a set signal to said first bistable circuit during period in which said first and second clock signals are not generated and said period in which said fourth latch means latches the output signal representing a reset state of said first bistable circuit. 
     
     
       3. A synchronizing circuit according to claim 1, in which said first bistable circuit is an R-S flip-flop. 
     
     
       4. A synchronizing circuit according to claim 1, in which said first latch means is a D type flip-flop having a data input terminal which is coupled to receive the output signal from said first bistable circuit, and a clock input terminal which is coupled to receive said first clock signal. 
     
     
       5. A synchronizing circuit according to claim 1, in which said second latch means is a D type flip-flop having a data input terminal which is coupled to receive the output signal from said first bistable circuit, and a clock input terminal which is coupled to receive said second clock signal. 
     
     
       6. A synchronizing circuit according to claim 2, in which said second bistable circuit is an R-S flip-flop. 
     
     
       7. A synchronizing circuit according to claim 2, in which said third latch means is a D type flip-flop having a data input terminal which is coupled to receive the output signal from said second bistable circuit, and a clock input terminal which is coupled to receive the logical sum of said first and second clock signals. 
     
     
       8. A synchronizing circuit according to claim 2, in which said fourth latch means is a D type flip-flop having a data input terminal which is coupled to receive the output signal from said first bistable circuit, and a clock input terminal which is coupled to receive the logical sum of said first and second clock signals. 
     
     
       9. A synchronizing circuit according to claim 1, in which said input pulse detecting circuit includes a delay circuit containing at least two inverters.