Parallel scan thermal camera

Abstract

The camera includes a chip of infrared detectors disposed in lines and a processing chip. The latter comprises integrators for integrating the output currents of the detectors, controlled by an automatic gain control loop for reducing the dynamic of the signal, delay lines, a summator for each line of detectors, error correction devices for reducing the fixed spatial noise errors, and a multiplexer receiving the signals associated with the various lines of detectors and furnishing a signal to a display device.

What is claimed is: 
     
       1. A thermal parallel scan camera including a chip of infrared detection diodes disposed in lines and a chip for processing the detection signals having means for integrating the output currents of the detectors and for delivering detection charge amounts associated with each of the lines of detectors, the two chips being hybridized, which camera further includes means for controlling the gain of the detected and processed siganls and means, including a conversion means, for converting the charges into voltages, connected to a reference voltage generator by a capacitive connection, and means for showing to the detection diodes a uniform reference background at a given temperature during each scan return, for determining, for each line of detectors, the difference between the detection charge amounts and the charge amounts associated with the reference background, the integration means comprising a first storage integrator and a second dump integrator connected alternately to their associated detector by a switch. 
     
     
       2. The camera as claimed in claim 1, wherein said control means are automatic gain control means adapted for controlling, as a function of the mean amplitude of the detected and processed signals, the means for integrating the output currents of the detectors. 
     
     
       3. The camera as claimed in claim 1, wherein said control means are adapted for controlling the integration time of said integration means by means of a clock with variable cyclic ratio. 
     
     
       4. The camera as claimed in claim 1, wherein means are provided, following the integration means, for rephasing the signals delivered by the detectors, integrated and controlled, and palliating the geometric dispersion of the detectors. 
     
     
       5. The camera as claimed in claim 1, wherein the information delivered by said means for determining the charge difference associated with the different lines of detectors respectively are multiplexed in a multiplexer connected to a display device. 
     
     
       6. The camera as claimed in claim 1, wherein the means for integrating the output currents of the detectors include input field effect transistors of the processing chip, connected directly to their respective detectors. 
     
     
       7. The camera as claimed in claim 6, wherein the input field effect transistors are integrated in a silicon substrate, they each include a storage well as drain and are each followed by a space arranged to be filled with minority carriers under the action of a transfer plate and a second storage well, the drain of the input transistors forming the source of dump field effect transistors. 
     
     
       8. The camera as claimed in claim 7, wherein the potential of the transfer plate is controlled by said gain control means. 
     
     
       9. The camera as claimed in claim 7, wherein the cathodes of output diodes in the silicon substrate are connected together by a voltage charge conversion line. 
     
     
       10. The camera as claimed in claim 7, wherein said silicon substrate includes multiplexing field effect transistors to the gates of which a reference voltage may be applied. 
     
     
       11. The camera as claimed in claim 10, wherein the multiplexing transistors each include an input diode to the cathode of which a multiplexing voltage is applied. 
     
     
       12. The camera as claimed in claim 11, wherein the voltage of the cathode of the input diodes of the multiplexing transistors and the voltage of their gate are controlled by a sensor sensing the position of a scanning mirror.