MOS temperature sensing circuit

Abstract

An MOS temperature sensing circuit formed on a silicon substrate which may be used for disabling portions of output drivers in EPROM at high temperatures. The circuit uses a first and second diode, one of which has substantially larger area than the other. The diodes are reverse biased through field-effect transistors. The leakage from the smaller diode is used to cancel the effects process variations on the leakage current of the larger diode, thereby providing a circuit with an output substantially dependent only on temperature.

I claim: 
     
       1. An MOS temperature sensing circuit formed on a silicon substrate comprising: a first and a second load;   a first and a second leakage device, coupled to said first and second loads, respectively, said loads biasing said leakage devices such that said devices each have a temperature dependent leakage current;   one of said first and second leakage devices having a greater substrate area than the other of said devices such that said one device draws more current at a higher temperature than said other device;   a differential amplifier means for detecting the difference in voltages coupled to said devices;   whereby a stable temperature sensing circuit is realized.   
     
     
       2. The circuit defined by claim 1 wherein one of said first and second loads provides an offset potential. 
     
     
       3. The circuit defined by claim 2 wherein said first and second leakage devices each comprises a diode. 
     
     
       4. The circuit defined by claim 3 wherein said first and second loads each comprise a field-effect transistor. 
     
     
       5. The circuit defined by claim 1 wherein a plurality of said circuits are fabricated on the same substrate. 
     
     
       6. The circuit defined in claim 5 including trimming means coupled to each of said circuits for adjusting a potential from one of said first and second leakage devices. 
     
     
       7. The circuit defined by claim 6 including trimming means for adjusting a voltage from one of said first and second leakage devices. 
     
     
       8. A MOS temperature sensing circuit formed on a silicon substrate comprising: a first and a second field-effect transistor;   a first and a second diode coupled to said first and second transistors, respectively, such that said first and second diodes are reverse biased, said first diode having a greater substrate area than said second diode;   a differential amplifier coupled to said first and second diodes;   whereby a stable temperature sensing circuit is realized.   
     
     
       9. The circuit defined by claim 8 wherein the periphery of said first diode is larger than the periphery of said second diode. 
     
     
       10. The circuit defined by claim 9 including trimming means for adjusting the potential from one of said first and second diodes. 
     
     
       11. The circuit defined by claim 10 including a plurality of said circuits formed on a single substrate. 
     
     
       12. An MOS temperature sensing circuit formed on a silicon substrate comprising: a first and a second field-effect transistor;   a first and a second diode coupled to said first and second transistors, respectively, such that said first and second diodes are reverse biased, the periphery of said first diode being greater than the periphery of said second diode;   a differential amplifier coupled to said first and second diodes;   whereby a stable temperature sensing circuit is realized.   
     
     
       13. The circuit defined by claim 12 wherein the area of said first diode is greater than the area of said second diode. 
     
     
       14. In a memory having a storage array and at least one output driver for providing an output data signal from said memory, an improvement comprising: a temperature sensing circuit for sensing the temperature of said memory comprising: a first and a second load; a first and a second leakage device coupled to said first and second loads, respectively, said loads biasing said leakage devices such that said devices each have a temperature dependent leakage current;   one of said first and second leakage devices having a greater substrate area than the other of said devices such that said one device draws more current at a higher temperature than said other device;   a differential amplifier means for detecting the difference in voltages coupled to said loads;       circuit means coupled to said driver and to said temperature sensing circuit such that a portion of said driver is disabled when the temperature of said memory drops to a predetermined temperature;   whereby the access time of said memory is improved.   
     
     
       15. In a memory having a storage array and at least one output driver for providing an output data signal from said memory, an improvement comprising: a temperature sensing circuit for sensing the temperature of said memory comprising; an MOS temperature sensing circuit formed on a silicon substrate comprising:   a first and a second field-effect transistor;   a first and a second diode coupled to said first and second transistors, respectively, such that said first and second diodes are reverse biased, said first diode having a greater substrate area than said second diode;   a differential amplifier coupled to said first and second diodes;     circuit means coupled to said driver and to said temperature sensing circuit such that a portion of said driver is disabled when the temperature of said memory drops to a predetermined temperature;   whereby the access time of said memory is improved.   
     
     
       16. The improvement defined by claims 14 or 15 wherein said memory comprises an electrically programmable read-only memory.