Parity checker circuit

Abstract

A parity checker circuit for performing a parity check in the serial transfer of data in an integrated circuit having an odd or even decision circuit receiving sequential bits constituting a data stream and generating an output signal having a level which becomes high or low and representing whether the number of "1" or "0" in the data is odd or even, and a parity flag circuit connected to receive the output signal from the decision circuit and operable in accordance with a write signal received simultaneously with the high or low level output signal and, in response to these signals, for outputting a parity flag indicative of the parity of the data.

What is claimed is: 
     
       1. A parity checker circuit for performing a parity check in the serial transfer of data in an integrated circuit comprising an odd or even decision circuit including a pair of feedback logic circuits, each comprising a plurality of logic gates and a transmission gate, said transmission gate being operable in accordance with said data stream so as to open or close said feedback logic circuits, wherein said odd or even decision circuit provides means for receiving sequential bits constituting a data stream and generating an output signal having a level which becomes high or low after reception of the data stream and representing whether the number of "1" or "0" in the data is odd or even, and a parity flag circuit connected to receive the output signal from said decision circuit and operable in accordance with a write signal received simultaneously with the high or low level output signal and, in response to said signals, for outputting a parity flag indicative of the parity of the data stream. 
     
     
       2. A parity checker circuit according to claim 1 further comprising means connected to said feedback logic circuits and operable in cooperation with said transmission gates for generating said output signal.