Multistatistics gatherer

Abstract

A subsystem component for use in an image processing system to compute a gray scale histogram function or various statistical functions relating to the coordinates of a region or regions in a binary image. A selected function is computed at the video rate of frame generation.

What is claimed is: 
     
       1. A statistical gatherer for use in an image processing system of the type that processes a digital image comprising a frame of pixels, with the positions of the lines in the frame indicated by a y coordinate and the position of a pixel in a given line indicated by an x coordinate, and with each pixel a digital value, the statistical gatherer comprising: an electronic RAM having an address input port for receiving an address signal identifying a selected storage location in said RAM, a data output port for transmitting a read signal encoding the value of a digital word stored in said selected storage location, and a data input port for receiving a write signal encoding the value of a digital word to be stored in the selected storage location;   address signal selection means, having an address select output port coupled to said address input port of said RAM and having a set of address select input ports for receiving signals, said address signal selection means for controllably coupling one of said address select input ports to said address select output port;   means for adding a selected increment to the digital word stored at the selected storage location in said RAM, said increment means having an increment signal input port and a read signal input port coupled to the data output of said RAM;   increment signal selection means, having an increment select signal output port coupled to the increment signal input port of said incrementing means and having a set of increment select input ports, said increment signal select means for controllably coupling one of said increment select signal input ports to said select increment signal output port;   a first pixel input coupled to a first one of said address select input ports and to a first one of said increment select input ports, said first pixel input for receiving a first digital pixel with the location of the first digital pixel in the image frame indicated by coordinates x and y;   means for generating a function output signal at a function output port, with the function output signal encoding a digital function value having a value f(x,y), and with said function output port coupled to a second one of said address select ports and a second one of said increment select ports.   
     
     
       2. The invention of claim 1 further comprising: a second digital pixel input coupled to a third one of said address select input ports and to a third one of said increment select input ports, said second pixel input for receiving a second pixel having coordinates x and y.   
     
     
       3. The invention of claim 2, wherein said RAM includes a write enable (WE) input, the invention further comprising: a TAG register; and   a comparator having a first input adapted to receive a selected part of said address signal, a second input coupled to said TAG register, and an output coupled to the WE input of said RAM.   
     
     
       4. The invention of claim 2 or 3 wherein the image processing system provides a handshake signal at the beginning of each frame and at the end of each line, said function generating means comprising: an accumulator for generating an accumulator value, the accumulator having a handshake input adapted to receive said handshake signal, an ACC output port, and an ACC input port;   a counter for generating a counter value, the counter having a handshake input, a CTR increment input port, and a CTR output port:   means, coupled to said CTR increment port, for selectively incrementing the counter value by one or two;   means for selectively adding either the counter value or a constant to the accumulator value, with the accumulator value being the output of said function generating means.   
     
     
       5. A statistical gatherer for use in an image processing system of the type that processes a digital image comprising a frame of pixels, with the positions of the lines in the frame indicated by a y coordinate and the position of a pixel in a given line indicated by an x coordinate, and with each pixel a digital value, the statistical gatherer comprising: an electronic RAM having an address input port for receiving an address signal identifying a selected storage location in said RAM, a data output port for transmitting a read signal encoding the value of a digital word stored in said selected storage location, and a data input port for receiving a write signal encoding the value of a digital word to be stored in the selected storage location;   an address signal MUX, having an address select output port coupled to said address input port of said RAM and having a set of address select input ports for receiving signals, said address signal MUX for controllably coupling one of said address select input ports to said address select output port;   an ALU, having a first ALU input port coupled to the data output port of said RAM for receiving said read signal, a second ALU input port for receiving an ALU input signal encoding an ALU input value, and an ALU output port coupled to data input port of said RAM;   means for controllably configuring said ALU to either add the ALU input value to the value encoded by the read signal or to compare a max/min value encoded by the read signal to the ALU input value and to modify said max/min value based on the outcome of said comparison;   an ALU input signal MUX, having an increment select signal output port coupled to the second ALU input port of said ALU and having a set of ALU select input ports, said ALU signal MUX for controllably coupling one of said ALU select signal input ports to said select ALU signal output port;   a first pixel input coupled to a first one of said address select input ports and to a first one of said ALU select input ports, said first pixel input for receiving a first digital pixel with the location of the first digital pixel in the image frame indicated by coordinates x and y;   means for generating a function output signal at a function output port, with the function output signal encoding a digital function value having a value f(x,y), and with said function output port coupled to a second one of said address select ports and a second one of said ALU select ports.   
     
     
       6. The invention of claim 5 further comprising: a second digital pixel input coupled to a third one of said address select input ports and to a third one of said ALU select input ports, said second pixel input for receiving a second pixel having coordinates x and y.   
     
     
       7. The invention of claim 6, wherein said RAM includes a write enable (WE) input, the invention further comprising: a TAG register; and   a comparator having a first input adapted to receive a selected part of said address signal, a second input coupled to said TAG register, and an output coupled to the WE input of said RAM.   
     
     
       8. A statistical gatherer for use in an image processing system of the type that processes a digital image comprising a frame of pixels, with the positions of the lines in the frame indicated by a y coordinate and the position of a pixel in a given line indicated by an x coordinate, and with each pixel a digital value, the statistical gatherer comprising: an electronic RAM having an address input port for receiving an address signal identifying a selected storage location in said RAM, a data output port for transmitting a read signal encoding the value of a digital word stored in said selected storage location, and a data input port for receiving a write signal encoding the value of a digital word to be stored in the selected storage location;   address signal selection means, having an address select output port coupled to said address input port of said RAM and having a set of address select input ports for receiving signals, said address signal selection means for controllably coupling one of said address select input ports to said address select output port;   means for comparing a max/min value, encoded in a max/min section of said digital word stored at the selected storage location, to a comparison value, encoded in a comparison input signal, to determine whether said max/min value is greater than or less than said comparison value, said comparison means having a comparison signal input port and a read signal input port coupled to the data output of said RAM;   means for modifying said max/min section based on the outcome of the comparison determination;   comparison signal selection means, having a comparison select signal output port coupled to the comparison signal input port of said comparing means and having a set of comparison select input ports, said comparison signal select means for controllably coupling one of said comparison select signal input ports to said comparison select signal output port;   a first pixel input coupled to a first one of said address select input ports and to a first one of said comparison select input ports, said first pixel input for receiving a first digital pixel with the location of the first digital pixel in the image frame indicated by coordinates x and y;   means for generating a function output signal at a function output port, with the function output signal encoding a digital function value having a value f(x,y), and with said function output port coupled to a second one of said address select ports and a second one of said comparison select ports.   
     
     
       9. The invention of claim 8 further comprising: a second digital pixel input coupled to a third one of said address select input ports and to a third one of said comparison select input ports, said second pixel input for receiving a second pixel having coordinates x and y.   
     
     
       10. The invention of claim 9, wherein said RAM includes a write enable (WE) input, the invention further comprising: a TAG register; and   a comparator having a first input adapted to receive a selected part of said address signal, a second input coupled to said TAG register, and an output coupled to the WE input of said RAM.   
     
     
       11. A statistical gatherer, for use in digital system, comprising: an electronic RAM having an address input port for receiving an address signal identifying a selected storage location in said RAM, a data output port for transmitting a read signal encoding the value of a digital word stored in said selected storage location, and a data input port for receiving a write signal encoding the value of a digital word to be stored in the selected storage location;   address signal selection means, having an address select output port coupled to said address input port of said RAM and having a set of address select input ports for receiving signals, said address signal selection means for controllably coupling one of said address select input ports to said address select output port;   means for adding a selected increment to the digital word stored at the selected storage location in said RAM, said increment means having an increment signal input port and a read signal input port coupled to the data output of said RAM;   increment signal selection means, having an increment select signal output port coupled to the increment signal input port of said incrementing means and having a set of increment select input ports, said increment signal select means for controllably coupling one of said increment select signal input ports to said select increment signal output port; and   a first digital input coupled to a first one of said address select input ports and to a first one of said increment select input ports, said first pixel input for receiving a first digital input signal.