Exchange with error correction

Abstract

A switching exchange in which data on each incoming line are applied to an encoder which produces redundant code words therefrom. The switching matrix is divided into n sub-switching matrices which each transmit a different sub-code word. The outputs of the sub-switching matrices are connected to a decoder which corrects erroneous data words and in addition indicates the occurrence of a fault. Each sub-switching matrix may have its own setting processor receiving identical setting information from a central switching processor. In the event of failure of a sub-switching matrix the decoder can correctly restore the data words. It therefore is possible to effet repair simply replacing the defective sub-switching matrix without switching-off the exchange.

What is claimed is: 
     
       1. In a switching exchange for computer-controlled switching of a plurality of lines each of which receives digital time-interleaved data, which exchange comprises a switching matrix which transmits the data in parallel in the form of data words comprising a plurality of data bits, the improvement characterized in that: the switching matrix (10) is preceded by an encoder (2) which from each data word produces a code word having a number of code bits exceeding the number of data bits of each data word and applies it to the switching matrix (10); the switching matrix is divided into a number of parallel sub-switching matrices (12, 14, 16, 18) which each transmit a sub-code word consisting of the bits of a portion of the code word; and the switching matrix is followed by a decoder (4, 4a) which produces the original data words from all the sub-code words; the code words and the sub-code words being structured so that when there is at least one mutilated sub-code word the decoder produces the correct data words and an error signal indicating the mutilated sub-code word. 
     
     
       2. A switching exchange as claimed in claim 1, wherein the number of bits of each code word is twice the number of bits of each data word. 
     
     
       3. A switching exchange is claimed in claim 1 wherein each sub-switching matrix (12, 14, 16, 18) has its own, setting computer (22, 24, 26, 28) and all the setting computers are controlled in parallel by a central switching control computer (6). 
     
     
       4. A switching exchange as claimed in claim 1, wherein the encoder (2) preceding the switching matrix (10) comprises at least two sub-encoders (32, 36) each of which receives a different portion of the data words and produces a sub-code word; each sub-switching matrix (12, 14, 16, 18) respectively transmits as a sub-code word the bits from a different portion of a sub-code word, so that all the sub-switching matrices transmit all the sub-code words; and the decoder subsequent to the switching matrix (10) consists of a number of sub-decoders (42,46) equal to the number of sub-encoders (32, 36), the sub-decoders being connected to the outputs of the switching matrix (10) such that each sub-decoder receives all the bits of a sub-code word and produces the corresponding portion of the data word. 
     
     
       5. A switching exchange as claimed in claim 1, wherein the error signal of the decoder is evaluated by a supervisory computer (8), further characterized in that: a fault memory (52) assigned to the decoder (4, 4a) is connected to the error signal outputs (F1 to F4) of the decoder (4, 4a) and to a counter (54) which identifies the transmission path through the switching matrix (10), said counter counting the data words within a frame; whereby upon the occurrence of an error signal such error signal and the identification of the transmission path are stored in the fault memory (52) and the supervisory computer (8) retrieves the content of the fault memory (52) and erases the fault memory. 
     
     
       6. A switching exchange as claimed in claim 5, characterized in that the fault memory (52) stores the signals of several sequentially occurring code word errors and the supervision computer (8) only erases the stored signals of the retrieved errors.