Stored logic program scanner for a data processor having internal plural data and instruction streams

Abstract

A program scanner for a processor having multiple internal streams of instruction and data flow scans a sequence of incoming codes, and employs a plurality of rams to detect various types of syllables in that code. The contents of these rams are signals indicating the various types of codes possible with the output of the rams then being multiplexed to provide an output indicating which syllables can be grouped together for transmission to various units of the processor.

What is claimed is: 
     
       1. A data processor coupled to an external memory and having multiple internal data and instruction streams to concurrently activate various units therein in response to a sequential string of object code syllables, said processor comprising: an execution unit to execute operator syllables in said object code;   a reference unit to execute external memory reference syllables in said object code; and   a program scanner including:   a scanning register having a plurality of parallel object code syllable positions to receive a portion of said string of object code;   a plurality of output registers coupled to said various units of said processor;   a switch network coupling the respective syllable positions of said scanning register to different ones of said output registers; and   a pluality of storage means, one for each of said syllable positions in said scanning register and coupled to said respective syllable positions to be addressed thereby, said respective storage means being coupled to said switch network and containing control signals indicating which of said syllable positions of said scanning register should be coupled to different ones of said output registers for concurrent transmission of the contents of said syllable positions to said different ones of said output registers.   
     
     
       2. A processor according to claim 1 further including: a central data buffer coupled to said execution unit, said reference unit and said output registers for data transfer therebetween.   
     
     
       3. A processor according to claim 2 wherein: said scanning register includes shift register means to shift to the lowered number syllable positions those syllables not transmitted to said output registers.   
     
     
       4. A processor according to claim 3 wherein said external memory stores strings of said object code and wherein; said scanning register is coupled to said external memory to receive a plurality of said object code syllables to fill unused syllable positions in said scan register.   
     
     
       5. A processor according to claim 4 wherein said program scanner further includes: syllable selection means to receive said strings of object code syllables for transmission to said scanning register; and   a program counter to specify how many syllables are to be supplied to said scanning register.   
     
     
       6. A processor according to claim 5 wherein said syllable selection means includes: a cache memory to receive said strings of object code syllables from said external memory and to store said object code syllables for future transmission to said scanning register; and   word selection means to receive from said cache memory means a plurality of said syllables forming a plurality of words and to select from said plurality of words the next syllables in a string of syllables for transmission to said scanning register.