Electronic display unit

Abstract

An electronic display unit according to this invention is formed of a plurality of display elements arranged in a two dimensional array. The display elements are selectively activated to generate a message. All the preselected display elements are activated and deactivated simultaneously. The message may be moved vertically or laterally across the array. A memory element is provided for activating each display element. Preferably the information from each memory element is simultaneously shifted laterally to an adjacent memory element while the display elements are disabled. A buffer is provided as an interface between each display element and the corresponding memory element. The intensity of each display element may be controlled by varying the power supply level to the buffer.

I claim: 
     
       1. A display unit comprising: a plurality of display elements arranged in an array of rows and columns;   a plurality of memory elements adapted to store information indicative of the status of said display element, each memory element being associated with one of said display elements, memory elements corresponding to each row being arranged and connected to pass said information to an adjacent memory element along a preselected direction;   control means for feeding said information into said memory elements; and   a plurality of FETs, each FET having a gate connected directly to a corresponding memory element, each of said FETs having a channel resistance and source to drain voltage controlled by a voltage on said gate indicative of the status of a respective display element, from said memory element to provide a feed-back to said gate thereby providing a constant current source to the corresponding display element for a uniform brightness.   
     
     
       2. The display unit of claim 1 wherein each memory element is adapted to activate a corresponding display element when receiving an enabling signal. 
     
     
       3. The display unit of claim 2 wherein each memory element is adapted to shift said information to an adjacent memory element of a corresponding row when receiving a clock signal. 
     
     
       4. The display unit of claim 3 wherein messages are shifted horizontally across said array by providing appropriate information to one of said memory elements of each row, shifting serially the information across each row and activating said display elements after each shift. 
     
     
       5. The display unit of claim 3 wherein messages are shifted vertically across said array by providing appropriate information to the memory elements of one of said rows, shifting said information to an adjacent row and activating the display elements after each row shift. 
     
     
       6. A display unit comprising: a plurality of boards, each board having: a plurality of display elements, said boards being arranged and constructed to form an array of display elements arranged in rows and columns,   a plurality of memory elements for storing information indicative of the status of an associated display element, said memory elements being connected in series to pass information from one memory element to an adjacent memory element in a preselected direction;     a plurality of FETs, each FEt having a gate connected directly to a corresponding memory element, each of said FETs having a channel resistance and source to drain voltage controlled by a voltage on said gate indicative of the status of a respective display element from said memory element to provide a feedback to said gate thereby providing a constant current source to the corresponding display element for a uniform brightness;   said boards being arranged and connected so that each row comprises several boards connected in series; and   control means for providing said information to said boards for generating a preselected message.   
     
     
       7. The display unit of claim 6 further wherein each board further comprises buffer means disposed between each memory element and the associated display element for driving said display element gating means for activating said buffer means when an enabling signal is received from said control means. 
     
     
       8. The display unit of claim 6 wherein said memory element is D-type latch. 
     
     
       9. The display unit of claim 7 wherein said buffer means comprises an FET. 
     
     
       10. The display unit of claim 7 wherein said display element is an LED. 
     
     
       11. The displaly unit of claim 6 wherein said control means is connected to one of the boards corresponding to each row and is adapted to provide a CLOCK signal for shifting information across each row concurrently to move a preselected message horizontally across the display. 
     
     
       12. The display unit of claim 6 wherein said control means is connected to one of the boards of one of said rows, said control means being adapted to generate a clock signal for shifting information across said rows, the boards of each row being connected to the boards of one of the adjacent rows to shift information in a preselected direction from one row to another in accordance with said clock signal, whereby a preselected message is shifted vertically across said display unit in a preselected direction.