Double polysilicon integrated circuit process

Abstract

In a double polysilicon integrated circuit processing method a first level polysilicon is used for FET gate fabrication, a second level is used for interconnection and both levels are used in the fabrication of analog capacitors over field oxide regions. By the invention, capacitors are also fabricated in the FET device well by implanting dopant through the second level polysilicon at the same time that dopant is implanted directly into other regions of the substrate to a greater depth and dopant level concentration so as to function as an FET source. The method is particularly adapted to fabricating DRAM memories.

What is claimed is: 
     
       1. A double polysilicon integrated circuit processing method comprising: (i) taking a silicon wafer;   (ii) forming field oxide regions therein;   (iii) forming a gate oxide layer over a device well region, said device well region having source, gate and capacitor areas;   (iv) depositing a first polysilcon layer over the gate oxide layer;   (v) etching the polysilicon to form a transistor gate over said gate area;   (vi) forming a second oxide layer over the gate and the surrounding device region;   (vii) depositing a second polysilicon layer over the second oxide layer;   (viii) etching the second polysilicon layer to leave polysilicon over said capacitor area; and   (ix) in a single implantation step, implanting ions through said second oxide layer into said source area to form a transistor source and through said oxide and second polysilicon layers to define one side of a capacitor at said capacitor area, said second level polysilicon at the capacitor area functioning as an opposed side of the capacitor, and the second oxide layer at the capacitor area functioning as a capacitor dielectric, the junction depth and concentration of ions in the capacitor area being less than the junction depth and concentration of ions in the source area.   
     
     
       2. A method as claimed in claim 1 wherein when etching said first level polysilicon to form the transistor gate, a region of said first level polysilicon is defined over the field oxide, when forming said second level oxide in the device region, a region of said second level oxide is formed over said first level polysilicon region, and when etching said second level polysilicon, a region thereof is defined over said second level oxide region, said regions of polysilicon and said oxide region comprising an analog capacitor. 
     
     
       3. A method as claimed in claim 1 wherein the substrate is a p-type substrate and the ions implanted are n-type. 
     
     
       4. A method as claimed in claim 3 wherein the ions implanted include a dose of arsenic ions and a dose of phosphorus ions. 
     
     
       5. A method as claimed in claim 1 wherein the implantation into the source area through oxide alone produces a doped region with sheet resistance of the order of 50 ohms per square and implantation into the capacitor area through oxide and polysilicon produces a doped region with sheet resistance of the order of 650 ohms per square. 
     
     
       6. A method as claimed in claim 1 in which the second layer of polysilicon is of a thickness substantially less than that of the first layer of polysilicon. 
     
     
       7. A method as claimed in claim 6 in which the first layer of polysilicon is of the order of 4000 Angstrom units thick and the second polysilicon layer is of the order of 1000 Angstrom units thick.