CMOS-inverter

Abstract

Reliable locking of a CMOS-inverter whose operating voltage lies in a high voltage range of approximately 20 V is provided when the circuit is activated with a CMOS-inverter of lower operating voltage. A normally-on n-channel MOS-FET whose control input is connected with the inverter output is connected in series with an MOS-FET of the CMOS-inverter.

I claim as my invention: 
     
       1. A CMOS-inverter system, comprising: a CMOS-inverter formed of a series connection of a normally off p-channel MOS-FET and a normally off N-channel MOS-FET having their drains connected in common and their gates connected in common, and a source of the normally off n-channel MOS-FET directly connecting to a reference potential;   the common drain connection being an output of the inverter and the common gate connection being an input of the inverter;   a normally on n-channel MOS-FET connected between a supply voltage and the p-channel MOS-FET, a control input of the normally on n-channel MOS-FET being connected to the output of the inverter; and   the supply voltage having a value higher than a high logic level of an input signal connected to said inverter input.   
     
     
       2. A CMOS-inverter system comprising: A CMOS-inverter formed of a series connection of a normally off p-channel MOS-FET and a normally off n-channel MOS-FET having their drains connected in common and their gates connected in common;   the common drain connection being an output of the inverter and the common gate connection being an input of the inverter;   a normally on n-channel MOS-FET connected in series with the p-channel MOS-FET, a control input of the normally on n-channel MOS-FET being connected to the output of the inverter; and   a first operating voltage lying in a high voltage range connecting to a drain of the normally on n-channel MOS-FET, and another CMOS inverter being provided connected to a relatively smaller second operating voltage, and whose output connects to an input of the CMOS-inverter.   
     
     
       3. A CMOS-inverter system according to claim 1 wherein the normally on n-channel MOS-FET is designed such that it is more weakly conductive relative to the normally off n-channel MOS-FET. 
     
     
       4. A system according to claim 3 wherein a ratio of channel width to channel length of the normally on n-channel MOS-FET is smaller than a ratio of channel width to channel length of the normally off n-channel MOS-FET. 
     
     
       5. A CMOS-inverter system according to claim 1 wherein the p-channel MOS-FET and series connected normally on n-channel MOS-FET are designed so as to be weakly conductive in relation to the normally off n-channel MOS-FET. 
     
     
       6. A system according to claim 5 wherein a ratio of channel width to channel length of the normally on n-channel MOS-FET and normally off p-channel MOS-FET is smaller than a ratio of channel width to channel length of the normally off n-channel MOS-FET. 
     
     
       7. A CMOS-inverter according to claim 1 wherein the normally off p-channel MOS-FET is dimensioned to be more weakly conductive than the normally off n-channel MOS-FET. 
     
     
       8. A CMOS-inverter system, comprising: a first high voltage CMOS-inverter formed of a series connection of a normally off n-channel MOS-FET and a normally off p-channel MOS-FET having their drains connected in common so as to form an output of the high voltage inverter and their gates being connected in common so as to form an input of the high voltage inverter;   a normally on n-channel MOS-FET having its drain connected to a relatively high operating voltage, its source connected to a source of the normally off p-channel MOS-FET, and its gate connected to the high voltage inverter output; and   a low voltage CMOS-inverter formed of first and second transistors connected to a low operating voltage lower than said high operating voltage, an output of the low-voltage inverter being connected to the input of the high-voltage inverter.