Data display arrangements

Abstract

A character memory of a data display arrangement is divided into a plurality of separate memory sections which are available to provide characters for display only for respective sub-areas of a display screen. The invention is especially suited to providing high resolution character-based displays using so-called dynamically redefinable characters sets. A memory map MM containing the memory sections is addressed by a counter COU. A latch L2 initially sets the counter COU to the address of the first memory section. During each line scanning period a ÷2 divider DV is responsive to character column pulses CP to step the counter COU to address a new memory section address evey second character position. At the end of each line scanning period line pulses LP reset the counter COU to the first memory section address. In a modification, the connections of the address bus between the counter and the memory map are altered so that the addresses as actually applied to the memory sections are only changed every second (or fourth) character position so that less memory is needed.

I claim: 
     
       1. A data display arrangement for displaying as an entity on a screen of a raster scan display device, a quantity of data represented by digital codes stored in a display memory and accessed repeatedly for the display in a recurrent cycle of scanning lines, the displayed data being composed of discrete characters organized in character rows each comprising a plurality of character positions, and each discrete character's shape being defined by selected dots of a dot matrix which constitutes a character format for the characters; said arrangement comprising a character memory for storing character information in bit pattern form and addressing means for selectively addressing said character memory in accordance with the stored digital codes to read out therefrom character information for the display; and wherein said character memory comprises a plurality of memory sections for storing character information representing DRCS character sets and said addressing means is operable to address a first one of said memory sections for a corresponding first portion of each line scanning period of the raster scan and is further operable to address at least one other of said memory sections for a further, or a respective further, corresponding portion of each said line scanning period thereby dividing said display into sub-areas, whereby DRCS characters stored in any one of said memory sections are available for display only in each sub-area of the screen that that memory section is individually identified with by such addressing. 
     
     
       2. A data display arrangement as claimed in claim 1, characterized in that each memory section has a capacity for storing as many DRCS characters as there are character positions in one of said sub-areas of the screen. 
     
     
       3. A data display arrangement as claimed in claim 2, characterized in that two or more sub-areas of th screen "share" the same DRCS character set as stored in a single memory section in the sense that any DRCS character of the set is available for display in any character position of either of said two or more sub-areas. 
     
     
       4. A data display arrangement as claimed in any one of claims 1, 2 or 3 further comprising at least one additional memory section which can accommodate an additional DRCS character set and which can be addressed by said addressing means so as to provide DRCS characters for display at any character position on the screen. 
     
     
       5. A data display arrangement as claimed in claims 1, 2 or 3, comprising logic and processor means for controlling the operation of the arrangement; characterized in that said addressing means is incorporated in said logic and processor means and includes a latch which in respect of a display using DRCS characters is latched to the address of said first memory section at the beginning of a raster scan, the addressing means further including a multi-bit address counter which is set by said latch to an initial count corresponding to said address of said first memory section, and divider means responsive to (column) pulses which identify character positions along a character row to step the counter to provide the addressess of said other memory sections in turn in response to every nth column pulse (n≧1), the counter being reset to its initial count at the beginning of each line scanning period. 
     
     
       6. A data display arrangement as claimed in claim 5, characterized in that said counter is stepped every second column pulse. 
     
     
       7. A data display arrangement as claimed in claim 5, characterized in that an address bus over which the memory section addresses are applied from the counter to address the DRCS memory sections comprises a plurality of bus connections which extend between a plurality of output terminals of the counter and a plurality of input terminals which are common to the memory sections, of which bus connections, the least significant bit output terminal of the counter is left unconnected and each of the other output terminals are connected respectively to the input terminal of one less significant bit value of the memory sections, leaving the most signficant bit input terminal unconnected. 
     
     
       8. A data display arrangement as claimed in claim 7, modified in that two or more least significant bit output terminals are left unconnected, to leave a corresponding number of most significant bit input terminals unconnected, the remaining output terminals being respectively connected to the remaining input terminals in accordance with their bit value order. 
     
     
       9. A data display arrangement as claimed in claim 1 further comprising at least one additional memory section which can accommodate an additional DRCS character set and addressable by said addressing means so as to provide DRCS characters for display at any character position on the screen, and logic and processor means for controlling the operation of the arrangement; characterized in that said addressing means is a part of said logic and processor means and includes a latch which for a display using DRCS characters is latched to the address of said first memory section at the beginning of a raster scan, the addressing means further including a multi-bit address counter which is set by said latch to an initial count corresponding to said address of said first memory section, and divider means responsive to (column) pulses which identify character positions along a character row to step the counter to provide the addresses of said other memory sections in turn in response to every n th  column pulse (n≧1), the counter being reset to its initial count at the beginning of each line scanning period.