Digital peak detector and method of peak detection

Abstract

A high-speed digital peak detector for determining the peak voltage of an input analog signal and for providing a one of N unary digital output corresponding to the peak voltage, where N is a positive integer, comprising a plurality of N self-latching voltage detectors in a flash-encoding or parallel encoding arrangement, each detector comprising a latchable differential voltage comparator and an Exclusive/Or gate, each of the comparators and gates having first and second input terminals and first and second output terminals and each of the comparators further having first and second latch function input terminals. The second output terminal of each of the comparators is connected to the first input terminal of a corresponding one of the gates, and the first and second output terminals of the corresponding one of the gates is connected, respectively, to the first and second latch function input terminals of the corresponding one of the comparators. A reset signal is coupled to the second input terminal of each of the gates and a standard voltage is coupled to the second input terminal of each of the comparators. A step difference from one standard voltage to the next is maintained which is substantially equal to a one/(N+1) part of the entire expected range of the input analog signal, the analog input signal being applied in parallel to the first input terminal of each of the comparators, and a one of N unary digital output being provided collectively at the N first output terminals of each of the N comparators corresponding to the peak voltage of the input analog signal.

What is claimed is: 
     
       1. A self-latching pulse amplitude detector for detecting a peak voltage level of an input pulse signal relative to a voltage of an externally provided standard signal, and for providing a resettable self-latched binary output signal corresponding thereto, comprising: comparator means for detecting said peak voltage level of said input pulse signal coupled thereto relative to a voltage of a standard signal coupled thereto, and for providing corresponding complementary first and second binary output signals therefrom, said comparator means having a first latch control input terminal;   means for providing a reset signal;   gate means having first and second input terminals for performing Exclusive/Or logic with respect to said second binary output signal coupled to said first input terminal and said reset signal coupled to said second input terminal, and for providing a corresponding first logic output signal resulting therefrom;   said corresponding first logic output signal being coupled to said first latch control input terminal of said comparator means for latching the first and second binary output signals from said comparator means when said peak voltage of said input pulse signal exceeds the voltage of said standard signal and thereafter unlatching said binary output signals in response to said reset signal, said first binary output signal thereby being a resettable self-latched binary output signal corresponding to the amplitude of said input pulse signal relative to the voltage of said standard signal.   
     
     
       2. The detector of claim 1, wherein: said gate means further providing a second logic output signal which is a logical complement of said first logic output signal; and   said comparator means further having a second latch control input terminal to which is coupled said second logic output signal from said gate means.   
     
     
       3. The detector of claim 1, wherein said comparator means comprises a latchable voltage comparator having differential inputs, complementary outputs, and complementary latch function inputs. 
     
     
       4. A self-latching pulse amplitude detector circuit for detecting an amplitude of an analog input signal relative to an externally provided standard voltage and for providing a self-latched binary output signal corresponding thereto, said circuit operating from a voltage supply providing supply and reference voltage levels at supply and reference terminals, respectively, comprising: a latchable differential voltage comparator having first and second comparator input terminals, first and second comparator output terminals, and first and second latch function input terminals;   said analog input signal coupled to said first comparator input terminal;   said standard voltage to be compared with said analog input signal coupled to said second comparator input terminal;   an Exclusive/Or gate having first and second gate input terminals, said first gate input terminal connected to said second comparator output terminal and having first and second gate output terminals connected to said first and second latch function input terminals, respectively; and   means coupled to said second gate input terminal for providing a reset signal thereto to cause said self-latching pulse amplitude detector circuit to reset upon external command;   said self-latched binary output signal being provided at said first comparator output terminal.   
     
     
       5. A high-speed digital peak detector for determining a peak voltage of an input analog signal and for providing a 1 of N unary digital outputs corresponding thereto, where N is a positive integer, said detector comprising: a plurality of N self-latching voltage detectors, each detector comprising a latchable differential voltage comparator and an Exclusive/Or gate, each of said comparators and gates having first and second input terminals and first and second output terminals and each of said comparators further having first and second latch function input terminals, the second output terminal of each of said comparators connected to the first input terminal of a corresponding one of said gates, and the first and second output terminals of said corresponding one of said gates connected respectively to the first and second latch function input terminals of said corresponding one of said comparators;   means coupled to the second input terminal of each of said gates for providing a reset signal thereto; and   means coupled to the second input terminal of each of said comparators for maintaining a standard voltage thereon, a step difference from one said standard voltage to the next which is substantially equal to a 1/(N+1) part of an entire expected range of said input analog signal;   said analog input signal being applied in parallel to said first input terminal of each of said comparators;   a 1 of N unary digital output being provided collectively at the first output terminals of each of said N comparators corresponding to the peak voltage of said input analog signal.   
     
     
       6. Apparatus for comparing a peak voltage level of an input analog pulse signal relative to a level of a standard voltage signal to produce a self-latching output and, subsequently, in response to an external command signal unlatching said output in a time period comparable to a pulse width of the input analog pulse signal, comprising: means for comparing an amplitude of said input analog pulse signal, with said standard voltage signal to produce a binary output signal and a logical complement of said binary output signal characterizing the comparison of said input and standard signals;   means for generating a binary reset signal responsive to said external command signal;   means for exclusive/or-ing said logical complement of said output binary signal with said binary reset signal to develop an output latch control signal;   means for self-latching said binary output signals in response to said output latch control signal; and   means for releasing said self-latched binary output signal and its logical complement by momentarily complementing said reset signal in response to said external command signal.   
     
     
       7. A method of comparing a peak voltage level of narrow pulses of an input analog signal relative to a level of a standard voltage signal to produce a self-latching output and, upon command, unlatching therefrom in a period comparable to a pulse width of the input analog signal, comprising the steps of: providing a latchable voltage comparator having first and second differential input terminals, input terminals for latch control, and first and second output terminals;   applying said input analog signal to said first differential input terminal;   applying said standard signal to said second differential input terminal;   producing a binary output signal and its complement at first and second output terminals, respectively, of said comparator corresponding to the differential comparison of said peak voltage level of pulses of said input analog signal with said level of said standard voltage signal;   coupling the complement of said comparator binary output signal to a first input terminal of an Exclusive/Or gate;   coupling an external reset command signal to a second input terminal of said Exclusive/Or gate;   performing an Exclusive/Or logic operation with respect to said signals on said first and second input terminals of said Exclusive/Or gate and providing an Exclusive/Or output logic signal corresponding thereto;   coupling said Exclusive/Or output signal to said input terminals for latch control on said voltage comparator in such polarity phase as to provide for self-latching of said comparator binary output signal in a logic "one" state if said peak voltage level of said input analog signal exceeds the level of said standard voltage signal;   releasing the latched comparator binary output signal in response to said external reset command signal by effecting a change in said Exclusive/Or output logic signal from a latching state to an unlatching state.   
     
     
       8. A method of comparing a peak voltage level of an input analog pulse signal relative to a level of a standard voltage signal to produce a self-latching output and, subsequently, in response to an external command signal, unlatching said output in a time period comparable to a pulse width of the input analog pulse signal, comprising the steps of: comparing an amplitude of said input analog pulse signal with said standard voltage signal to produce a binary output signal and its logical complement characterizing the comparison of said input and standard signals;   generating a binary reset signal responsive to said external command signal;   exclusive/or-ing the logical complement of said output binary signal with said binary reset signal to develop an output latch control signal;   self-latching said binary output signal and its complement in response to said output latch control signal; and   releasing said self-latched binary output signal and its logical complement by momentarily complementing said reset signal in response to said external command signal.