Device for superimposition of the successive stages of the transfer of data among several data processing units
Abstract
A control logic circuit (C) is provided in each unit such as processors andemories in a multiple processor data processing system. Each control logic circuit (C) is equipped with a priority circuit (P12) which at one input receives the eligible local calls (RQ i L) of the unit itself and at the other input receives external calls (RQ k ) transmitted by the other units. The control logic circuit (C) enables control by its unit of a transmission but only when its priority circuit (P12) recognizes that unit as having the highest priority among the other units. The logic circuit (C) together with a T circuit (13) selects local calls as a function of the state of occupation of the data lines of the transmission bus.
Claims
exact text as granted — not AI-modifiedI claim:
1. A system for superposing successive phase of data transfer on a transmission bus having data, address and control sections common to a plurality of data processing units, each said unit including a control logic circuit, comprising: a programmed control means; means responsive to said control means for establishing a multiple cycle operating phase of said unit; means for storing data to be transmitted on the data section of the bus to another one of said units or to be received from said another one of said units and for storing an address of said another one of said units; means responsive to said control means for applying to the bus a unit status signal indicating any utilization of the bus by said unit itself; means responsive to the control means for generating a local request signal requesting access to the bus during a current operating phase of the unit; first monitoring means monitoring said bus and responsive to the control means for generating a bus occupation signal to determine whether the bus currently is in utilization by another one of said units; said control means including second monitoring means monitoring said bus for generating a status signal depending upon bus status defining utilization of the bus by said unit for subsequent cycles of the same operating phase of the unit itself; priority means monitoring said bus and said local request signal for measuring priorities of the local request signal and request signals on the bus generated respectively by other ones of said units, and in response for generating a priority local request signal if the priority of the local request signal is determined to be the highest; first cycle generator means controlled by said multiple cycle operating phase establishing means responsive to a priority local request signal and said second monitoring means for controlling said unit to transmit data stored in said storage means to said another one of the units on the bus; and second cycle generator means controlled by said multiple cycle operating phase establishing means and responsive to said priority local request signal for controlling said unit to receive data from said another one of said units on the bus.
2. The system of claim 1, wherein each said unit includes means responsive to said control means and operative during a second cycle of the first cycle generator for transmitting onto the control section of said bus data defining the length of data to be transmitted by said unit itself.
3. The system of claim 1, wherein each said unit includes means controlled by said second cycle generator means and operative during a first cycle of the second cycle generator means for transmitting onto the address section of said bus an address of said another one of said units.
4. The system of claim 1, wherein each said unit further includes means responsive to said first cycle generator and operative during a first cycle of the first cycle generator means for controlling and reading data stored in said another one of said units.Join the waitlist — get patent alerts
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