Modular self-routing PCM switching network for distributed-control telephone exchange

Abstract

An automatic exchange of a telephone system comprises a PCM switching network with a plurality of cascaded stages for establishing temporal and spatial connections between incoming channels on input lines of the first stage and outgoing channels on output lines of the last stage in response to commands from external controllers dialoguing with internal controllers of the network. Pairs of switching matrices forming part of nonadjacent stages are combined into modular switching units each provided with its own internal controller. Routing instructions are transmitted from an external controller to a first internal controller which selects a signal path through the matrices of its own switching unit and informs a second internal controller of that selection whereupon the latter extends the path through an adjoining switching unit, and so on until the connection is completed. With digital message words such as speech bytes traveling in a forward direction from the input side to the output side of the network, the instruction words pertaining thereto move in the opposite direction over the same interstage links; the two paths are mutually conjugate within each switching unit, their matrices being bypassed by the routing instructions.

We claim: 
     
       1. In an automatic exchange of a telecommunication system for the selective transfer of exclusively PCM messages from a multiplicity of input lines to a like multiplicity of output lines, in combination: a switching network divided into an odd number exclusively of timedivision stages each including a plurality of switching matrices individually connectable in cascade with matrices of an adjoining stage to set up forward-signaling paths for the transmission exclusively of PCM message words from given input lines to selected output lines, matrices of nonadjoining stages on opposite sides of a middle stage being structurally united into matrix pairs;   external control means for commanding the establishment and disestablishment of exclusively temporal connections between incoming and outgoing PCM channels by way of forward-signaling paths set up by said matrices; and   internal control means responsive to commands from said external control means for selectively establishing and selectively disestablishing said connections, said internal control means including common controllers for respective matrix pairs of said nonadjoining stages and central controllers for matrices of said middle stage, said internal control means further including ancillary circuitry bypassing the cascaded matrices for the transmission of routing instructions between said external control means, said common controllers and said central controllers in a direction opposite that of message-word transmission via interstage links forming part of said forward signaling paths.   
     
     
       2. The combination defined in claim 1 wherein each of said interstage links include transceivers disposed upstream and downstream of each matrix. 
     
     
       3. The combination defined in claim 2 wherein said ancillary circuitry includes, for any forward-signaling path set up by a common controller of a matrix pair through one matrix of said pair, the transceivers disposed downstream and upstream of the other matrix of said pair. 
     
     
       4. The combination defined in claim 3 wherein each PCM channel is part of a channel group having respective time slots assigned thereto in a recurrent frame marked by accompanying synchronization pulses, a predetermined time slot of said frame being assigned to a virtual channel for the transmission of routing instructions in said opposite direction from the downstream transceiver of said other matrix to said common controller and from the latter to the upstream transceiver of said other matrix. 
     
     
       5. The combination defined in claim 4 wherein said ancillary circuitry further includes storage means inserted between said common controller and the transceivers of said other matrix. 
     
     
       6. The combination defined in claim 5, further comprising timing means responsive to said synchronization pulses for serializing instruction words passing from said downstream transceiver to said storage means in said predetermined time slot and pertaining to a plurality of channel groups passing simultaneously through said one matrix, said storage means being controlled by said timing means to emit outgoing instruction words during said predetermined time slot to said upstream transceiver. 
     
     
       7. The combination defined in claim 6 wherein said ancillary circuitry further comprises a converter inserted between said storage means and said downstream and upstream transceivers, said converter being controlled by said timing means for serializing incoming instruction words emitted by the downstream transceiver during said predetermined time slot and parallelizing stored instruction words sent during said predetermined time slot to the upstream transceiver. 
     
     
       8. The combination defined in claim 7 wherein said converter comprises a multiplicity of shift registers jointly loadable in said predetermined time slot with incoming instruction words from the downstream transceiver and consecutively loadable in further time slots of a frame with stored instruction words to be sent to the upstream transceiver, first multiplexer means responsive to signals from said timing means for controlling the loading of said shift registers, and second multiplexer means responsive to signals from said timing means for controlling the unloading of said shift registers with sequential readout of the incoming instruction words to said storage means and with concurrent readout of the stored instruction words to the upstream transceiver. 
     
     
       9. The combination defined in claim 8 wherein said predetermined time slot is the first slot of a frame, said second multiplexer means directly conveying to said storage means an instruction word appearing on one output of said downstream transceiver during said first time slot. 
     
     
       10. The combination defined in claim 9 wherein the number of said shift registers is one less than half the number of time slots per frame, said first and second multiplexer means being controlled by said timing means to establish communication between said storage means and respective shift registers during every other time slot following said first time slot. 
     
     
       11. The combination defined in claim 2, further comprising a pair of samplers connected across each matrix for extracting message words entering and leaving the respective matrix in an established path segment at instants separated by the transit time of said segment, said samplers being connected to the controller associated with the respective matrix for enabling a comparison of the extracted message words by said associated controller to verify the continuity of said path segment. 
     
     
       12. The combination defined in claim 11 wherein said ancillary circuitry further includes interface means activable by the associated controller, in response to a mismatch between the extracted bytes, for checking on the presence of a continuity-indicating test code emitted by the downstream transceiver of a matrix paired with said respective matrix.