Digital to analog converter employing sigma-delta modulation for use in telephone systems

Abstract

A digital to analog converter is employed in the digital line circuit of a telephone system and operates to convert a digital signal indicative of an analog speech signal back into a replica of the analog signal. The converter operates with an interpolated input digital signal to detect by means of a sign bit, the characteristic of an input digital word as being indicative of a positive or negative level. An error correcting signal is provided by the converter which is added to the next digital word to provide a compensated word having a sign bit determined by the remainder and the sign bit of the previous digital word. This word is then processed in sequence to produce an output pulse stream from the sign detector indicative of successive positive or negative values as defined by the input digital words, each of which are modified according to the error correcting signal.

We claim: 
     
       1. A sigma-delta digital to analog converter for converting a digital signal to an analog signal, said digital signal having a given word rate and comprising a plurality of digital words each having the same number of given bits, and each digital word being indicative of the weighted value of said analog signal, with at least one bit in each digital word being a sign bit indicating whether said digital word and therefore said weighted value of said word is a positive value or a negative value with respect to a given digital signal level comprising: first adding means having an output, a first input for receiving each of said digital words serially according to said given word rate and a second input to receive an error correcting signal to provide at said output modified digital words, each having a sign bit indicative of a remainder of a preceding digital word;   sign detecting means coupled to said output of said first adding means responsive to each of said modified digital words to provide an output signal therefrom including an output pulse of one bit length to indicate when said sign bit of each of said modified words indicates one of said positive value and said negative value and no output pulse when said sign bit of each of said modified words indicates the other of said positive value and said negative value;   feedback control means including a second adding means having an output, a first input coupled to said output of said first adding means and a second input coupled to the output of said sign detecting means to invert said output signal of said sign detecting means and to add said inverted output signal of said sign detecting means to said modified digital words at said output of said first adding means to provide said correcting signal and delay means coupled between said output of said second adding means and said second input of said first adding means to couple said correcting signal to said first adding means to cause each successive digital word applied to said first input of said first adding means to be modified to provide said modified digital words whereby each successive digital word received by said first adding means is modified by said correcting signal based on said sign bit of said preceding digital word to cause said sign detecting means to provide said output signal for each of said modified digital words and   low pass filter means coupled to the output of said sign detecting means for providing a replica of said analog signal from said output signal of said sign detecting means.   
     
     
       2. A converter according to claim 1 wherein said digital signal has a word rate in excess of one million words per second with each word having at least three bits.   
     
     
       3. A converter according to claim 1 wherein said analog signal is a voice band signal having a frequency range from 0 to 4 KHz.   
     
     
       4. A converter according to claim 1 wherein said first adding means includes a register for storing said modified digital words, with one bit as stored indicative of said sign bit.   
     
     
       5. A converter according to claim 1 wherein a positive (binary one) sign bit indicates a negative weighted value and a negative (binary zero) sign bit indicates a positive weighted value.   
     
     
       6. A converter according to claim 1 wherein said digital signal is derived from an interpolator in a receive path of a digital line circuit and operative to increase the word rate of a received digital signal to said given word rate and to reduce the number of bits N in said received digital signal to said number of given bits.   
     
     
       7. A sigma-delta digital to analog converter arrangement for converting a digital signal to an analog signal, said digital signal having a given word rate and comprising a series of digital words each having the same given number of bits and each digital word being indicative of the weighted value of said analog signal, with at least one bit in each digital word being a sign bit indicating whether said digital word and therefore said weighted value is a positive value or a negative value with respect to a given digital signal level comprising: interpolating means having said digital signal coupled thereto for increasing said given word rate to a second higher word rate to provide a second digital signal at the output of said interpolating means;   means coupled to said interpolating means resposive to said second digital signal for selecting a predetermined number of said given number of bits of each word less than said given number including said sign bit to provide a third digital signal at said second word rate at the output of said means for selecting, with each word of said third digital signal having the same number of said selected predetermined number of bits;   first adding means having an output, a first input for receiving said third digital signal and a second input to receive an error correcting signal, said first adding means adding to said words in said third digital signal said error signal to provide said output of said first adding means modified digital words each having a sign bit representative of a remainder of a preceding digital word;   sign detecting means coupled to said output of said first adding means responsive to said modified words for providing an output signal therefrom including an output pulse when said sign bit of each of said modified words indicates one of said positive value and said negative value and no output pulse when said sign bit of each of said modified words indicates the other of said positive value and said negative value;   feedback control means including a second adding means having an output, a first input coupled to said output of said first adding means and a second input coupled to the output of said sign detecting means to invert said output signal of said sign detecting means and to add said inverted output signal of said sign detecting means to said modified digital words at said output of said first adding means to provide said error signal and delay means coupled between said output of said second adding means and said second input of said first adding means for application of said error signal to said first adding means to cause each successive digital word of said third digital signal to be modified by said error signal based on said sign bit of said prededing digital word to cause said sign detecting means to provide said output signal for each word in said third digital signal; and   low pass filter means coupled to the output of said sign detecting means for providing a replica of said analog signal from said output signal of said sign detecting means.   
     
     
       8. An arrangement according to claim 7 wherein said digital signal as applied to said interpolating means has a word rate of about 32 KHz, with at least 13 bits per word.   
     
     
       9. An arrangement according to claim 8 wherein said second higher word rate is above 1MHz.   
     
     
       10. An arrangement according to claim 8 wherein said selected predetermined number of bits of said words of said third digital signal is at least three bits per word, but less than 13 bits per word.   
     
     
       11. An arrangement according to claim 7 wherein said analog signal is a voice signal within a bandwidth of relatively 0 to 4 KHz.   
     
     
       12. An arrangement according to claim 7 wherein each of said output pulse of said sign detecting means is of the same amplitude.   
     
     
       13. An arrangement according to claim 7 wherein said digital signal is a PCM signal in a receive path of a telephone line circuit.