Apparatus for measuring program execution

Abstract

A measuring apparatus for measuring the time of execution of instructions or the number of cycles that addresses are within a selected address range of a memory. The measurement includes a measurement of any common subroutines that have been called by the instructions within the selected range. The measuring apparatus includes range circuitry connected to the address bus of the memory that detects instruction addresses within the selected range and instruction addresses within a common range having the common subroutines. The measuring apparatus further includes link logic for controlling a counter to both measure the instructions within the selected range and measure instructions within the common range when they immediately follow the selected range on the address bus. In the preferred embodiment, the memory is organized in ranges so that the first range begins at the first memory location in the memory and the last range ends at the last memory location in the memory. Any one of the ranges can be designated as a common range. The counter circuitry includes a plurality of counters, one associated with each of the ranges. Each counter can measure instruction addresses within its associated range and instruction addresses within a common range that immediately follow its associated range.

I claim: 
     
       1. An apparatus for measuring the execution of instructions, each of the instructions stored in a memory at a memory location having a memory address associated therewith, the memory being accessed by a memory bus for carrying memory addresses thereon, said apparatus comprising: range detection means connected to said memory bus and responsive to the memory addresses thereon for detecting memory addresses within a first range and memory addresses within a second range;   counter means enabled in response to said range detection means for incrementing said counter means at least once for each presence on said memory bus of a memory address within said first range; and   link logic means connected to said range detection means and said counter means for enabling said counter means to also be incremented at least once for each presence of a memory address within said second range when an address within said second range is on said memory bus immediately following an address within said first range.   
     
     
       2. The apparatus of claim 1, further comprising second counter means associated with said second range and enabled in response to said range detection means for incrementing said second counter means at least once for each presence on said memory bus of a memory address within said second range. 
     
     
       3. The apparatus of claim 1, wherein the instructions in the memory are arranged in a plurality of ranges, including said first and second ranges, wherein said range detection means detects memory addresses within each one of said plurality of ranges in addition to said first and second ranges, and wherein said apparatus further comprises a separate counter means associated with each one of said plurality of ranges in addition to said first range; each said separate counter means being incremented at least once for each presence on said memory bus of a memory address within the associated one of said plurality of ranges.   
     
     
       4. The apparatus of claim 3, wherein each memory address falls within one of said plurality of ranges, and wherein the first address within one of said ranges is the beginning address of the memory, and the ending address of another of said plurality of ranges is the ending address of said memory. 
     
     
       5. The apparatus of claim 1, wherein said range detection means is provided with predetermined range limit addresses indicating the address limits of said first and second ranges, and wherein said range detection means includes at least one comparator for comparing the range limit addresses to the addresses carried on said memory bus. 
     
     
       6. The apparatus of claim 1, wherein said counter means includes a binary counter, said counter being periodically incremented during a period of time that an instruction within said first range is on said memory bus and an instruction within said second range is on said memory bus immediately following an instruction within said first range. 
     
     
       7. An apparatus for measuring the execution of instructions stored at memory locations within the memory of a data processing system comprising: range detection means for receiving an address associated with each of the memory locations for detecting memory addresses within a first range;   counter means connected to said range detection means and enabled in response thereto for incrementing said counter means at least once for each memory address received within said first range;   said range detection means including means for detecting memory addresses within a second range; and   linking means connected to said range detection means for enabling said counter means to be incremented at least once for each memory address received within said second range when an instruction within said second range immediately follows an instruction within said first range.   
     
     
       8. The apparatus of claim 7 in which said memory includes a plurality of software modules, each said software module having a plurality of instructions which perform when executed a major function in the data processing system, said memory also including at least one common subroutine having a plurality of instructions which are executed during the execution of at least some of said software modules, and wherein all the instructions of one of said software modules are within said first range and all of the instructions within said one common subroutine are within said second range. 
     
     
       9. The apparatus of claim 7, wherein the memory locations of the memory are arranged in a plurality of ranges, wherein the first memory location of one of said ranges is the beginning memory location in the memory, wherein the last memory location of another of said ranges is the last memory location in the memory, wherein each memory location in the memory is accessed by an associated address on a memory bus connected to the memory, and wherein the range detection means comprises module range logic connected for receiving the address on said memory bus and providing range indicating bits for indicating which of said plurality of ranges the address on said memory bus is within. 
     
     
       10. The apparatus of claim 9, further comprising means for supplying common range bits and also comprising common range logic for receiving said common range bits indicating which of said plurality of ranges is said second range, said common range logic being connected to said module range logic for receiving said range indicating bits and for providing a common match bit at its output indicating when the address on said memory bus is within said second range. 
     
     
       11. The apparatus of claim 10, wherein said range detection means comprises a comparator associated with each of said first and second ranges, each said comparator for receiving a range limit address signal indicating the address limits of its associated range and for receiving the address on said memory bus, and for comparing the range limit address signal to the address on said memory bus to determine if the address on said memory bus falls within its associated range. 
     
     
       12. An apparatus for measuring the time of execution of software instructions stored at memory locations in the memory of a data processing system, wherein each memory location is accessed by an associated memory address carried on an address bus connected to the memory, the measuring apparatus comprising: module range logic connected to said address bus for receiving each memory address carried thereon and connected for receiving a plurality of range limit addresses that define a plurality of address ranges within the memory, wherein the number of address ranges is one greater than the number of range limit addresses, and wherein one of said address ranges begins at the same address as the first memory location in the memory, and another of said address ranges ends at the same address as the last memory location in the memory, said module range logic including a plurality of comparators, the number of said comparators being the same as the number of range limit addresses, each of said comparators receiving one of said range limit addresses and the memory address on the memory address bus for comparing its one of said range limit addresses to the memory address and providing output signals indicating whether the memory address is less than, equal to, or greater than its one of said range limit addresses, and logic circuitry for receiving the outputs of each of said comparators and providing range indicating bits, each of said range indicating bits corresponding to one of said address ranges and indicating whether the memory address is within its corresponding address range;   common range logic for receiving the range indicating bits from said module range logic and for receiving a plurality of common range bits that each corresponds to one of said address ranges and that indicate if its corresponding address range is a common range, said common range logic providing at its output a common match bit indicating whether the memory address carried on the memory bus is within the common range;   link logic for receiving a plurality of common link bits, each common link bit associated with one of said address ranges and indicting whether a measurement of addresses within its associated one of said address ranges is to have included therein a measurement of addresses within the common range indicated by the common range bits for receiving the common match bit, and for receiving the range indicating bit from said module range logic, said link logic for providing a measurement enabling bit for each of said address ranges;   a buffer register for receiving and storing each measurement enabling bit;   said link logic including an AND gate and a paired OR gate associated with each one of said address ranges, each AND gate receiving the common match bit, the common link bit of its associated address range, and the previous measurement enabling bit of its associated range stored in said buffer register, each OR gate receiving the output of its AND gate and the range indicating bit of its associated address range, each said OR gate providing the measurement enabling bit of its associated range for storage in said buffer register; and   counter circuitry, including a counter associated with each of said address ranges and enabled by the measurement enabling signal of its associated address range, so that each said counter maintains a count representing a measurement of time that addresses within its associated range are on the memory bus and if its associated common link bit indicates that a measurement of the time that addresses within the common range is to be included, such measurement of time that the addresses are within the common range is included in the last-named counter if an address within the common range immediately follows an address within the associated address range on the memory bus.   
     
     
       13. The apparatus of claim 12, wherein said counter circuitry further includes counter control logic for receiving each measurement enabling signal and for controlling each said counter, said counter control logic providing a clocking signal to each said counter during the period of time in which addresses within its associated range are on the memory bus. 
     
     
       14. An apparatus for measuring the time required for executing instructions from a memory; each said instruction being stored in said memory at a memory location having a memory address associated therewith; said instructions being grouped into a plurality of software modules and at least one common software module, said instructions being accessed by a memory bus which carries memory addresses thereon; said apparatus comprising: range detection means connected to said memory bus and being responsive to the memory addresses thereon for determining which one of said plurality of software modules including said common software module is being executed;   counter means connected to said range detection means for producing a count which reflects the time required for executing the instructions associated with one of said plurality of software modules as determined by said range detection means; and   link logic means connected to said range detection means and said counter means for increasing the count on said counter means to correspond to the time required for executing the instructions associated with said common software module when an address from said common software module is placed on said memory bus immediately after an address from one of said plurality of software modules is placed thereon.