Bipolar time modulated encoder/decoder system

Abstract

An encoder/decoder is described which allows data transmission on an A.C. coupled transmission system. The encoder converts a serial data stream comprised of combinations of logical "1"'s and "0"'s in an NRZ format to an output pulse train. The latter is characterized not only by phase reversal for each bit of data, as required for A.C. coupled systems, but by bit durations which are dissimilar for a logic "1" and "0". The encoded data is transmitted and subsequently applied to the decoder which restores the data to an NRZ format, and provides a corresponding series of clock pulses for interpreting the data. The encoder/decoder may be implemented in a simple logic configuration.

What is claimed is: 
     
       1. An encoder/decoder system for encoding an NRZ data stream of two unipolar voltage levels to bipolar time-modulated data pulses and for decoding the latter comprising: an encoder portion of said encoder/decoder system, said encoder portion including programmable counter means having a plurality of input terminals and an output terminal, a source of clock pulses, means for applying said NRZ data and said clock pulses respectively to a first and a second of said plurality of input terminals, said voltage levels of said NRZ data conditioning said counter means to count a respective pair of different predetermined numbers of clock pulses before generating signal pulses on said output terminal thereof,   a first bistable means coupled to said output terminal of said counter means and being switched alternately between opposite stable states in response to the occurrence of said signal pulses, said first bistable means having an output terminal, said bipolar time-modulated data pulses appearing on the latter terminal,   a decoder portion of said encoder/decoder system, said decoder portion including a pair of comparator means each having a pair of input terminals and an output terminal, delay means having an input terminal and a pair of output terminals,   means coupling the output terminal of said first bistable means in common to an input terminal of each of said pair of comparator means and to said input terminal of said delay means, the pair of output terminals of said delay means being coupled respectively to the other input terminals of each of said comparator means, the delay in said data pulses provided by said delay means between said input terminal and said pair of output terminals thereof corresponding respectively to the time intervals for counting said pair of different predetermined numbers of clock pulses,   each of sad comparator means generating a pulse on said output terminal thereof in response to the concurrence of data signals on its respective input terminals,   a second bistable means having set and reset terminals and an output terminal, means coupling the respective output terminals of said comparator means to said set and reset terminals, the signals appearing on the output terminal of said second bistable means in response to the setting and resetting thereof representing decoded data, and logic means coupled to said set and reset terminals for generating clock-type pulses in concurrence with said decoded data.   
     
     
       2. An encoder/decoder system as defined in claim 1 further characterized in that said output terminal of said counter means is coupled to a third of said plurality of input terminals thereof, each of said signal pulses appearing on said last mentioned output terminal effecting the resetting of said counter means. 
     
     
       3. An encoder/decoder system as defined in claim 2 wherein said first bistable means is a toggle-type flip-flop. 
     
     
       4. An encoder/decoder system as defined in claim 3 wherein each of said pair of comparator means is an exclusive-NOR logic gate. 
     
     
       5. An encoder/decoder system as defined in claim 4 further characterized in that said means couplng the respective output terminals of said comparator means to said set and reset terminals of said second bistable means comprises a pair of AND gates each having a pair of input terminals and an output terminal, said output terminal of each of said comparator means being connected to an input terminal of one of said AND gates, a pair of delay lines, each of said delay lines being interposed between said output terminal of a comparator means and the other input terminal of one of said AND gates, the output terminals of said AND gates being connected respectively to said set and reset terminals of said second bistable means. 
     
     
       6. An encoder/decoder system as defined in claim 5 wherein said second bistable means is a set/reset-type flip-flop. 
     
     
       7. An encoder/decoder system as defined in claim 4 wherein said logic means for providing means clock-type pulses in said decoder portion is an OR gate, said OR gate having a predetermined delay from each of said input terminals to said output terminal thereof. 
     
     
       8. An encoder/decoder system as defined in claim 7 wherein the delays in said data pulses provided by said delay means are respectively time intervals corresponding to two and three times the period of said clock pulses. 
     
     
       9. An encoder/decoder system as defined in claim 8 wherein the delay in each of the delay lines interposed between one of said comparator means and one of said AND gates is equal to one half the period of said clock pulses. 
     
     
       10. An encoder/decoder system as defined in claim 9 characterized in that said means coupling the output terminal of said first bistable means in common to an input terminal of each of said pair of comparator means and to said input terminal of said delay means includes fiber optic transmission line means.