Circuit and method for generating a ramp signal

Abstract

Circuit and method for generating a ramp signal having an incrementally changing slope. The invention is particularly useful for ramping magnetic recording bias or erase signals by providing a relatively slow slope within the non-linear region of the magnetic medium characteristic while providing a relatively steep slope in the linear region to reduce recording of disturbing "pop" signals.

What is claimed is: 
     
       1. A circuit for generating a ramp signal, comprising: a source for providing a first D.C. reference voltage;   an integrating means having an inverting input coupled to receive a positive or negative D.C. input step voltage for responsively coupling said inverting input to said D.C. reference voltage or ground, respectively, having a non-inverting input coupled to receive a predetermined ratio of said D.C. reference voltage and having an output coupled to provide said ramp signal in response to said D.C. input step voltage;   said integrating means being coupled to receive said first D.C. reference voltage and to limit a maximum value of said ramp signal provided thereby to a value determined by said D.C. reference voltage;   said integrating means having a series input resistor coupled between an input terminal for receiving said input step voltage and said inverting input and having a feedback capacitor coupled between said output and said inverting input of said integrating means and having a predetermined number of further input resistors and switch means respectively, each further input resistor being coupled in parallel to said series input resistor via one said switch means; and   a detecting means coupled to detect in succession predetermined magnitudes of said ramp signal and to apply respective control signals in response to each said magnitude obtained by said ramp signal to activate said switch means in said succession.   
     
     
       2. The circuit of claim 1 wherein said integrating means has a predetermined time constant determined by respective values of said series input resistor and capacitor and wherein for an increasing ramp signal said switches are controlled in a first succession to incrementally decrease said time constant and for a decreasing ramp signal said switches are controlled in a second succession opposite to said first succession to inrementally increase said time constant. 
     
     
       3. The circuit of claim 2 wherein for said increasing ramp signal said switches are controlled to connect in said first succession said respective further resistors to said series input resistor and for said decreasing ramp signal said switches are controlled to disconnect in said second succession said respective further resistors from said series input resistor. 
     
     
       4. The circuit of claim 3 further comprising a first resistive voltage divider means having one terminal coupled to said output of said first D.C. reference voltage source, having a second, opposite terminal grounded and having an output terminal provided between said first and second terminal, respectively, said output terminal being coupled to said non-inverting input of the integrating means. 
     
     
       5. The circuit of claim 4 wherein respective resistance values between said first and said output terminal and between said second and said output terminal of said resistive voltage divider means are selected equal to obtain a time interval necessary for ramping-up equal to that which is necessary for ramping-down said ramp signal. 
     
     
       6. The circuit of claim 1 wherein said detecting means comprises means for comparing voltage levels obtained by said ramp signal with respective predetermined further D.C. voltage reference values each obtained as a respective predetermined ratio of said first reference voltage. 
     
     
       7. The circuit of claim 6 wherein said detecting means comprises a predetermined number of voltage comparators and voltage divider means, each voltage comparator having a first non-inverting input coupled to said output of said integrating means and a second inverting input coupled to an output of said voltage divider means, respectively, each said voltage divider means having a first terminal coupled to an output of said source for providing said first D.C. reference voltage and having a second, opposite terminal grounded, and wherein an output of each said voltage comparator is coupled to a control input of one said switch means. 
     
     
       8. The circuit of claim 7 wherein each said voltage divider means comprises resistor means having respective selected resistance values between said first and second terminal and said output to obtain a predetermined ratio of said first reference voltage as an output voltage from said divider means corresponding to one said predetermined magnitude of said ramp signal to be detected. 
     
     
       9. The circuit of any of claims 1 to 8 wherein said source for providing said D.C. reference voltage is an adjustable voltage source. 
     
     
       10. A circuit for generating an adjustable ramp signal, comprising: an adjustable D.C. reference voltage source having an output coupled to provide a desired adjustable first D.C. reference voltage;   a first means having an input coupled to receive said adjustable first D.C. reference voltage and having an output coupled to provide a predetermined ratio thereof;   an integrating means having an inverting input coupled to receive a positive or negative D.C. input step voltage for responsively coupling said inverting input to said adjustable first D.C. reference voltage or ground, respectively, having a non-inverting input coupled to said output of said first means for receiving said predetermined ratio of said adjustable first D.C. reference voltage and having an output coupled to provide said ramp signal in response to said D.C. input step voltage;   said integrating means being further coupled to receive said adjustable first D.C. reference voltage and to limit a maximum value of said ramp signal provided thereby to a value determined by said adjustable first D.C. reference voltage;   said integrating means having a series input resistor coupled between an input terminal for receiving said input step voltage and said inverting input and having a feedback capacitor coupled between said output and said inverting input of said integrating means and having a predetermined number of further input resistors and switch means respectively, each further input resistor being coupled in parallel to said series input resistor via one said switch means; and   a means coupled to detect in succession predetermined magnitudes of said ramp signal and to apply respective control signals in response to each said magnitude obtained by said ramp signal to activate said switch means in said succession.   
     
     
       11. The circuit of claim 10 wherein said first means comprises a resistive voltage divider means having one terminal coupled to said output of said adjustable D.C. reference voltage source, having a second, opposite terminal grounded and having a third terminal provided between said first and second terminal, respectively, corresponding to said output of said first means and wherein a resistance value between said first and third terminal and between said second and third terminal of said resistive voltage divider means is selected equal to obtain a time interval necessary for ramping-up equal to that which is necessary for ramping-down said ramp signal with respect to said maximum value. 
     
     
       12. A circuit for generating an adjustable ramp signal, comprising; an adjustable D.C. reference voltage source having an output coupled to provide a desired adjustable D.C. reference voltage value;   a first resistive voltage divider means having a first terminal coupled to said output of said adjustable D.C. reference voltage source having a second, opposite terminal grounded, and having a third, output terminal provided between said first and second terminal, respectively;   an integrating means having an inverting input coupled to receive a postive or negative D.C. input step voltage for responsibly coupling said inverting input to said adjustable first D.C. reference voltage or ground, respectively, having a non-inverting input coupled to said output terminal of said voltage divider means for receiving a predetermined ratio of said adjustable first D.C. reference voltage value and having an output coupled to provide said ramp signal in response to said D.C. input step voltage;   said integrating means being further coupled to receive said adjustable first D.C. reference voltage and to limit a maximum value of said ramp signal provided thereby to a value determined by said adjustable first D.C. reference voltage;   said integrating means having a series input resistor coupled between an input terminal for receiving said input step voltage and said inverting input and a feedback capacitor coupled between said output and said inverting input of said integrating means and having a predetermined number of further input resistors and switch means respectively, each further input resistor being coupled in parallel to said series input resistor via one said switch means; and saod corciot further comprising:   a predetermined number of voltage comparators coupled to detect in succession predetermined magnitudes of said ramp signal and voltage divider means, each voltage comparator having a first non-inverting input coupled to said output of said integrating means and a second inverting input coupled to an output of said voltage divider means, respectively, each said voltage divider means having a first terminal coupled to an output of said adjustable D.C. reference source and having a second, opposite terminal grounded, and wherein an output of each said voltage comparator is coupled to a control input of one said switch means.   
     
     
       13. A circuit for generating an adjustable ramp signal, comprising: an adjustable D.C. reference voltage source having an output coupled to provide a desired adjustable first D.C. reference voltage;   a first means having an input coupled to receive said adjustable first D.C. reference voltage and having an output coupled to provide a predetermined ratio thereof;   an integrating means having an inverting input coupled to receive a positive or negative D.C. input step voltage for responsively coupling said inverting input to said adjustable first D.C. reference voltage or ground, respectively, having a non-inverting input coupled to said output of said first means for receiving said predetermined ratio of said adjustable first D.C. reference voltage and having an output coupled to provide said ramp signal in response to said D.C. input step voltage;   said integrating means being further coupled to receive said adjustable first D.C. reference voltage and to limit a maximum value of said ramp signal provided thereby to a value determined by said adjustable first D.C. reference voltage;   said integrating means having a series input resistor couled betwen an input terminal for receiving said input step voltage and said inverting input and having a feedback capacitor coupled between said output and said inverting input of said integrating means and having a predetermined number of further input resistors and switch means respectively, each further input resistor being coupled in parallel to said series input resistor via one said switch means; and   a detecting means coupled to detect predetermined magnitudes of an increasing ramp signal in a first succession and to apply responsively respective control signals to said switches to connect is sasid first succession said further resistors respectively to said series input resistor to obtain an incrementally increasing slope of said increasing ramp signal and said detecting means being coupled to detect said predetermined magnitudes of a decreasing ramp signal in a second succession, opposite to said first succession and to apply responsively respective control signals to said switches to disconnect in said second succession said further resistors respectively from said series input resistor to obtain an incrementally decreasing slope of said decreasing ramp signal.   
     
     
       14. A method of providing a ramp signal, comprising the steps of: providing a first D.C. reference voltage;   providing a predetermined ratio of said first D.C. reference voltage;   providing an increasing or decreasing integrated D.C. ramp voltage respectively, in response to a D.C. input step signal having a selected integrating time constant corresponding to a selected slope of said ramp voltage;   limiting said D.C. ramp voltage to a maximum value determined by said first D.C. reference voltage;   detecting in succession predetermined magnitudes obtained by said increasing or decreasing D.C. ramp voltage; and   successively increasing or decreasing in predetermined increments the slope of said ramp voltage, respectively, in response to detected predetermined magnitudes obtained by said respectively increasing or decreasing ramp signal.   
     
     
       15. The method of claim 14 wherein said step of successively increasing or decreasing the slope of said ramp voltage, respectively, is provided by successively decreasing or increasing said selected integrating time constant, respectively in predetermined increments. 
     
     
       16. The method of claim 15 wherein said first D.C. reference voltage is adjustable.