High withstand voltage structure of a semiconductor integrated circuit

Abstract

A vertical PNP transistor having a large withstand voltage is disclosed. On a P-type substrate, a N-type epitaxial layer is provided. A P-type isolation region is formed in the epitaxial layer as a closed-loop to isolate a portion of the epitaxial layer from the other portions thereof. A first N-type buried layer is formed in the isolated epitaxial layer at the interface of the epitaxial layer and the semiconductor layer so as to separate the two. A second P-type buried layer is provided on top of the first buried layer. A P-type collector region is formed as a second closed-loop in the epitaxial layer enclosed within the first closed-loop. A high N-type concentration region that permits great withstand voltage is formed as a closed-loop separating the first closed-loop and the second closed-loop regions. A P-type emitter region is formed in the epitaxial layer region enclosed within the second closed-loop. Without the emitter region, the device can be used as a diode. By adding a N-type region within the emitter region, an NPNP thyristor can be obtained.

What is claimed is: 
     
       1. A semiconductor device comprising: a semiconductor substrate (11) of one conductivity type;   a semiconductor layer (15) of the other conductivity type;   an isolation region (13, 16) of said one conductivity type formed as a closed-loop to isolate a portion of said semiconductor layer from other portions of said semiconductor layer, said isolation region penetrating said semiconductor layer to reach said semiconductor substrate;   a first buried layer (12) of said other conductivity type formed in the vicinity of the interface between said semiconductor substrate and the isolated portion of said semiconductor layer;   a second buried layer (14) of said one conductivity type formed in the vicinity of the interface between said first buried layer and said isolated portion of said semiconductor layer;   a first region (17) of said one conductivity type formed as a closed-loop to isolate a part of said isolated portion from other parts of said isolated portion, said first region extending from the outer surface of said isolated portion to the interface between said isolated portion and said second buried region;   a second region (19) of said other conductivity type formed in said isolated portion between said isolation region and said first region, said second region extending from the outer surface of said isolated portion to said first buried region, having an upper portion overlapped with said isolation region and said first region and having an impurity concentration higher than the impurity concentration of said semiconductor layer.   
     
     
       2. A semiconductor device as claimed in claim 1, said semiconductor device further comprising a third region (18) of said one conductivity type formed in said isolated part of said semiconductor layer, whereby said second buried layer, said first region, said isolated part and said third region form a transistor. 
     
     
       3. A semiconductor device as claimed in claim 2, wherein said second region has an impurity concentration at least three times that of the impurity concentration of said semiconductor layer. 
     
     
       4. A semiconductor device as claimed in claim 1, wherein said isolation region has an upper part (16) and a lower part (13), said upper part extending from the outer surface of said semiconductor layer, said lower part rising from the interface between said semiconductor layer and said semiconductor substrate, and said upper part and said lower part contacting with each other in said semiconductor layer. 
     
     
       5. A semiconductor device as claimed in claim 4, wherein said second region has an impurity concentration at its outer surface lower than that of said upper part of said isolation region. 
     
     
       6. A semiconductor device as claimed in claim 1, wherein said second region has an impurity concentration at least three times that of the impurity concentration of said semiconductor layer. 
     
     
       7. A semiconductor device as claimed in claim 1, wherein said second region has an impurity concentration at its outer surface lower than that of said isolation region.