Synchronization apparatus and method

Abstract

Synchronization apparatus and method for maintaining synchronization between a binary encoded signal and a timing signal generated in the apparatus and employed in processing the binary encoded signal. The synchronization apparatus includes an up/down binary counter operative to sample the binary encoded signal at a predetermined rate and to count upwardly for each sample of the binary encoded signal having the first logic value and to count downwardly for each sample of the binary encoded signal having the second logic value. A timing signal generated within the synchronization apparatus and including a plurality of pairs of timing pulses is employed to ascertain the values of the counts in the up/down counter at the times of each pair of timing pulses. The values of these counts are examined over a period of several (e.g., 8) pairs of the timing pulses to determine whether the binary encoded signal is in synchronism with, leads, or lags the timing signal. If a lead or lag situation is determined to exist, the timing relationship of the binary encoded signal and the timing signal is altered to bring the signals back into synchronism.

What is claimed is: 
     
       1. A synchronization apparatus comprising: sampling counter means arranged to receive a binary encoded signal of a predetermined rate and an associated sample clock signal of a predetermined rate, said binary encoded signal comprising bits of first and/or second logic values;   timer means arranged to receive the aforesaid sample clock signal and operative to produce a timing signal of a rate twice that of the binary encoded signal, said timing signal comprising a series of successive pairs of pulses A and B;   said sampling counter means being capable of counting in positive and negative directions and being operative to sample the binary encoded signal at the rate of the sample clock signal and to count upwardly in binary fashion in response to each sample of the binary encoded signal having the first logic value and to count downwardly in binary fashion in response to each sample of the binary encoded signal having the second logic value;   first means operative at the occurrence of each A pulse of the timing signal produced by the timer means to retain the then existing binary count of the sampling counter means, said count having a positive or negative signed value expressed by A i , and to multiply the value of said count by a factor of 2 thereby to provide a resultant quantity expressed by 2A i , and further operative at the occurrence of each B pulse of the timing signal produced by the timer means to retain the then existing binary count of the sampling counter means, said count having a positive or negative signed value and expressed by B i  ; and   second means associated with the first means and arranged to receive each set of the quantities expressed by 2A i  and B i  corresponding to each pair of pulses A and B, said second means being operative to calculate a value and associated positive or negative sign for the expression represented by ##EQU3##  where i, M and K are positive integers, i has a value of 1 to M, and sign B i  represents the positive or negative sign of the quantity B i , said second means being further operative to produce and apply a signal having a value and associated sign as calculated from the foregoing expression to the timer means for altering the timing relationship between the binary encoded signal and the timing signal produced by the timing means by an amount and direction in accordance with said value and associated sign.   
     
     
       2. A synchronization apparatus in accordance with claim 1 wherein the second means comprises: third means operative for each set of values for 2A i  and B i  corresponding to each pair of pulses A and B to subtract the value of 2A i  from B i  and to multiply the resultant quantity by the positive or negative sign of B i , thereby to provide a resultant quantity expressed by C i  ;   fourth means operative to retain and to add together M successive values of C i  for i=1 to M, thereby to provide a sum expressed by ##EQU4##  where M is a positive integer and sign B i  represents the positive or negative sign of the quantity B i  ;   fifth means operative to derive an average of the M summed values of C i , said average being a quantity expressed by ##EQU5## sixth means operative to divide the average derived by the fifth means by a quantity K, where K is a positive integer, and to produce and apply to the timer means a signal having a value and associated sign as derived from the division operation for altering the timing relationship between the binary encoded signal and the timing signal produced by the timing means by an amount and direction in accordance with said value and associated sign.   
     
     
       3. A synchronization apparatus in accordance with claim 2 wherein: K has a value of 2.   
     
     
       4. A synchronization apparatus in accordance with claim 2 wherein: the first means, fourth means, fifth means and sixth means include a storage register.   
     
     
       5. A synchronization apparatus in accordance with claim 4 wherein the third means comprises: first circuit means operative for each set of values for 2A i  and B i  corresponding to each pair of pulses A and B to subtract the value of 2A i  from B i , thereby to provide a resultant quantity; and   second circuit means operative to multiply each resultant quantity provided by the first circuit means by the positive or negative sign of B i , thereby to provide a resultant quantity expressed by C i .   
     
     
       6. A synchronization apparatus in accordance with claim 5 wherein: the first circuit means includes an adder circuit; and   the second circuit means includes a true-complement circuit.   
     
     
       7. A synchronization apparatus in accordance with claim 5 wherein: K has a value of 2.   
     
     
       8. A synchronization apparatus in accordance with claim 4 wherein: the third and fourth means include adder means operative for each set of values for 2A i  and B i  corresponding to each pair of pulses A and B to subtract the value of 2A i  from B i  and to add together the M successive values of C i  for i=1 to M.   
     
     
       9. A synchronization apparatus in accordance with claim 8 wherein: M has a value of 8; and   K has a value of 2.   
     
     
       10. A synchronization apparatus in accordance with claim 2 wherein the first means includes: running count register means operative to receive and retain therein a running count and sign of the sampling counter means during the sampling operations of the sampling counter means;   "A" register means operative at the occurrence of each A pulse of the timing signal produced by the timer means to retain the then existing binary count of the sampling counter means, said count having a positive or negative signed value expressed by A i , and to multiply the value of said count by a factor of 2 to provide a resultant quantity expressed by 2A i  ; and   "B" register means operative at the occurrence of each B pulse of the timing signal produced by the timer means to retain the then existing binary count of the sampling counter means, said count having a positive or negative signed value expressed by B i .   
     
     
       11. A synchronization apparatus in accordance with claim 10 wherein the third means comprises: first circuit means coupled to the "A" and "B" register means of the first means and operative for each set of values of 2A i  and B i  retained in the "A" and "B" register means corresponding to each pair of pulses A and B to subtract the value of 2A i  from B i , thereby to provide a resultant quantity; and   second circuit means coupled to the first circuit means and operative to multiply each resultant quantity provided by the first circuit means by the positive or negative sign of B i , thereby to provide a resultant quantity expressed by C i .   
     
     
       12. A synchronization apparatus in accordance with claim 11 wherein the fourth means comprises: "C" storage means coupled to the second circuit means of the third means and operative to receive and retain therein in succession M successive quantities C i  ; and   third circuit means coupled to the "C" storage means and operative to add together the M quantities C i  retained in the "C" storage means for i=1 to M, thereby to provide a sum expressed by ##EQU6##   
     
     
       13. A synchronization apparatus in accordance with claim 12 wherein: a fifth means includes: first divide means coupled to the third circuit means of the fourth means and operative to derive a value for the expression ##EQU7## the sixth means includes: second divide means coupled to the first divide means and to the timer means and operative to derive a value for the expression ##EQU8##  and to produce and apply to the timer means a signal having a value and associated sign as calculated from the foregoing expression for altering the timing relationship between the binary encoded signal and the timing signal produced by the timing means by an amount and direction in accordance with said value and associated sign.     
     
     
       14. A synchronization apparatus in accordance with claim 13 wherein: the first circuit means of the third means includes an adder circuit;   the third circuit means of the fourth means includes an adder circuit;   the first divide means of the fifth means includes register means for deriving the value and associated sign of the expression ##EQU9## the second divide means of the fixth means includes register means for deriving the value and associated sign of the expression ##EQU10## M has a value of 8; and K has a value of 2.   
     
     
       15. A synchronization method comprising the steps of: providing a binary encoded signal of a predetermined rate and an associated sample clock signal of a predetermined rate, said binary encoded signal comprising bits of first and/or second logic values;   producing a timing signal of a rate twice that of the binary encoded signal, said timing signal comprising a series of successive pairs of pulses A and B;   sampling the logic values of the bits of the binary encoded signal at the rate of the sample clock signal and counting the samples in a running count fashion in both positive and negative directions, the count of the samples increasing in an upward direction for each sample of a bit of the binary encoded signal having the first logic value and decreasing in a downward direction for each sample of a bit of the binary encoded signal having the second logic value;   deriving the counts provided in the previous step at the time of occurrence of each A and B pulse, each of said counts having a positive or negative signed value and being expressed by A i  and B i , respectively, and multiplying the value of A i  by a factor of 2 thereby to provide a resultant quantity expressed by 2A i  ;   receiving each set of quantities represented by 2A i  and B i  corresponding to each pair of pulses A and B and calculating a value and associated positive or negative sign for the expression represented by ##EQU11##  where i, M and K are positive integers, i has a value of 1 to M, and sign B i  represents the positive or negative sign of the quantity B i  ; and   altering the timing relationship between the binary encoded signal and the timing signal by an amount and direction in accordance with the value and associated sign as calculated from the expression set forth in the previous step.   
     
     
       16. A synchronization method in accordance with claim 15 wherein: K has a value of 2.   
     
     
       17. A synchronization method in accordance with claim 15 wherein the deriving and multiplying step comprises the steps of: obtaining and retaining each count provided in the sampling and counting step at the time of occurrence of each A pulse, said count having a positive or negative signed value and being expressed by A i  ;   multiplying the value of A i  by a factor of 2 thereby to provide a resultant quantity expressed by 2A i  ; and   obtaining and retaining each count provided in the sampling and counting step at the time of occurrence of each B pulse, said count having a positive or negative signed value and being expressed by B i .   
     
     
       18. A synchronization method in accordance with claim 16 wherein the receiving and calculating step comprises the steps of: receiving each set of quantities represented by 2A i  and B i  corresponding to each pair of pulses A and B and subtracting the value of 2A i  from B i , thereby to derive an absolute resultant quantity expressed by |(B i  -2A i )|; and   multiplying the resultant quantity |(B i  -2A i )| derived in the previous step by the positive or negative sign of B i  thereby to provide a resultant quantity expressed by   C.sub.i =|(B.sub.i -2A.sub.i)|B.sub.sign B.sbsb.i,        where sign B i  is the positive or negative sign of the quantity B i .   
     
     
       19. A synchronization method in accordance with claim 18 wherein the receiving and calculating step further comprises the steps of: receiving and retaining M successive values of C i  for i=1 to M, where i and M are positive integers;   adding together the M successive values of C i , from i=1 to M, thereby to provide a resultant quantity expressed by ##EQU12## dividing the resultant quantity derived in the previous step by M thereby to obtain an average of the M summed values of C i , said average being represented by the expression ##EQU13## and dividing the average derived in the previous step by K thereby to derive a quantity having a value and associated sign represented by the expression ##EQU14##  where K is a positive integer.   
     
     
       20. A synchronization method in accordance with claim 19 wherein: M has a value of 8; and   K has a value of 2.